2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 * Copyright (C) 2014-2016, Toradex AG
5 * copied from nitrogen6x
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <environment.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/mx6-ddr.h>
21 #include <asm/bootm.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/mach-imx/sata.h>
27 #include <asm/mach-imx/boot_mode.h>
28 #include <asm/mach-imx/video.h>
29 #include <dm/platform_data/serial_mxc.h>
30 #include <dm/platdata.h>
31 #include <fsl_esdhc.h>
33 #include <imx_thermal.h>
34 #include <linux/errno.h>
41 #include "../common/tdx-cfg-block.h"
42 #ifdef CONFIG_TDX_CMD_IMX_MFGR
46 DECLARE_GLOBAL_DATA_PTR
;
48 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
53 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
56 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
67 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
69 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
70 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
74 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
77 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
78 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
79 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
81 #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
83 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
85 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
89 /* use the DDR controllers configured size */
90 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
91 (ulong
)imx_ddr_size());
97 iomux_v3_cfg_t
const uart1_pads_dce
[] = {
98 MX6_PAD_CSI0_DAT10__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
99 MX6_PAD_CSI0_DAT11__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
101 iomux_v3_cfg_t
const uart1_pads_dte
[] = {
102 MX6_PAD_CSI0_DAT10__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
103 MX6_PAD_CSI0_DAT11__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
),
106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
108 struct i2c_pads_info i2c_pad_info1
= {
110 .i2c_mode
= MX6_PAD_CSI0_DAT9__I2C1_SCL
| PC
,
111 .gpio_mode
= MX6_PAD_CSI0_DAT9__GPIO5_IO27
| PC
,
112 .gp
= IMX_GPIO_NR(5, 27)
115 .i2c_mode
= MX6_PAD_CSI0_DAT8__I2C1_SDA
| PC
,
116 .gpio_mode
= MX6_PAD_CSI0_DAT8__GPIO5_IO26
| PC
,
117 .gp
= IMX_GPIO_NR(5, 26)
121 /* Apalis local, PMIC, SGTL5000, STMPE811 */
122 struct i2c_pads_info i2c_pad_info_loc
= {
124 .i2c_mode
= MX6_PAD_KEY_COL3__I2C2_SCL
| PC
,
125 .gpio_mode
= MX6_PAD_KEY_COL3__GPIO4_IO12
| PC
,
126 .gp
= IMX_GPIO_NR(4, 12)
129 .i2c_mode
= MX6_PAD_KEY_ROW3__I2C2_SDA
| PC
,
130 .gpio_mode
= MX6_PAD_KEY_ROW3__GPIO4_IO13
| PC
,
131 .gp
= IMX_GPIO_NR(4, 13)
135 /* Apalis I2C3 / CAM */
136 struct i2c_pads_info i2c_pad_info3
= {
138 .i2c_mode
= MX6_PAD_EIM_D17__I2C3_SCL
| PC
,
139 .gpio_mode
= MX6_PAD_EIM_D17__GPIO3_IO17
| PC
,
140 .gp
= IMX_GPIO_NR(3, 17)
143 .i2c_mode
= MX6_PAD_EIM_D18__I2C3_SDA
| PC
,
144 .gpio_mode
= MX6_PAD_EIM_D18__GPIO3_IO18
| PC
,
145 .gp
= IMX_GPIO_NR(3, 18)
149 /* Apalis I2C2 / DDC */
150 struct i2c_pads_info i2c_pad_info_ddc
= {
152 .i2c_mode
= MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL
| PC
,
153 .gpio_mode
= MX6_PAD_EIM_EB2__GPIO2_IO30
| PC
,
154 .gp
= IMX_GPIO_NR(2, 30)
157 .i2c_mode
= MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA
| PC
,
158 .gpio_mode
= MX6_PAD_EIM_D16__GPIO3_IO16
| PC
,
159 .gp
= IMX_GPIO_NR(3, 16)
164 iomux_v3_cfg_t
const usdhc1_pads
[] = {
165 MX6_PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
166 MX6_PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
167 MX6_PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
168 MX6_PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
169 MX6_PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
170 MX6_PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
171 MX6_PAD_NANDF_D0__SD1_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
172 MX6_PAD_NANDF_D1__SD1_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
173 MX6_PAD_NANDF_D2__SD1_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
174 MX6_PAD_NANDF_D3__SD1_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
175 MX6_PAD_DI0_PIN4__GPIO4_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
), /* CD */
176 # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
180 iomux_v3_cfg_t
const usdhc2_pads
[] = {
181 MX6_PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
182 MX6_PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
183 MX6_PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
184 MX6_PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
185 MX6_PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
186 MX6_PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
187 MX6_PAD_NANDF_CS1__GPIO6_IO14
| MUX_PAD_CTRL(NO_PAD_CTRL
), /* CD */
188 # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
192 iomux_v3_cfg_t
const usdhc3_pads
[] = {
193 MX6_PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
194 MX6_PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
195 MX6_PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
196 MX6_PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
197 MX6_PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
198 MX6_PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
199 MX6_PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
200 MX6_PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
201 MX6_PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
202 MX6_PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
203 MX6_PAD_SD3_RST__GPIO7_IO08
| MUX_PAD_CTRL(WEAK_PULLUP
),
206 int mx6_rgmii_rework(struct phy_device
*phydev
)
208 /* control data pad skew - devaddr = 0x02, register = 0x04 */
209 ksz9031_phy_extended_write(phydev
, 0x02,
210 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW
,
211 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
212 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
213 ksz9031_phy_extended_write(phydev
, 0x02,
214 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW
,
215 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
216 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
217 ksz9031_phy_extended_write(phydev
, 0x02,
218 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW
,
219 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x0000);
220 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
221 ksz9031_phy_extended_write(phydev
, 0x02,
222 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW
,
223 MII_KSZ9031_MOD_DATA_NO_POST_INC
, 0x03FF);
227 iomux_v3_cfg_t
const enet_pads
[] = {
228 MX6_PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
229 MX6_PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
230 MX6_PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
231 MX6_PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
232 MX6_PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
233 MX6_PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
234 MX6_PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
235 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
236 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
237 MX6_PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
238 MX6_PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
239 MX6_PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
240 MX6_PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
241 MX6_PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
242 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
243 /* KSZ9031 PHY Reset */
244 MX6_PAD_ENET_CRS_DV__GPIO1_IO25
| MUX_PAD_CTRL(NO_PAD_CTRL
),
245 # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
248 static void setup_iomux_enet(void)
250 imx_iomux_v3_setup_multiple_pads(enet_pads
, ARRAY_SIZE(enet_pads
));
253 static int reset_enet_phy(struct mii_dev
*bus
)
255 /* Reset KSZ9031 PHY */
256 gpio_direction_output(GPIO_ENET_PHY_RESET
, 0);
258 gpio_set_value(GPIO_ENET_PHY_RESET
, 1);
263 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
264 iomux_v3_cfg_t
const gpio_pads
[] = {
265 /* Apalis GPIO1 - GPIO8 */
266 MX6_PAD_NANDF_D4__GPIO2_IO04
| MUX_PAD_CTRL(WEAK_PULLUP
),
267 MX6_PAD_NANDF_D5__GPIO2_IO05
| MUX_PAD_CTRL(WEAK_PULLUP
),
268 MX6_PAD_NANDF_D6__GPIO2_IO06
| MUX_PAD_CTRL(WEAK_PULLUP
),
269 MX6_PAD_NANDF_D7__GPIO2_IO07
| MUX_PAD_CTRL(WEAK_PULLUP
),
270 MX6_PAD_NANDF_RB0__GPIO6_IO10
| MUX_PAD_CTRL(WEAK_PULLUP
),
271 MX6_PAD_NANDF_WP_B__GPIO6_IO09
| MUX_PAD_CTRL(WEAK_PULLUP
),
272 MX6_PAD_GPIO_2__GPIO1_IO02
| MUX_PAD_CTRL(WEAK_PULLDOWN
),
273 MX6_PAD_GPIO_6__GPIO1_IO06
| MUX_PAD_CTRL(WEAK_PULLUP
),
274 MX6_PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(WEAK_PULLUP
),
277 static void setup_iomux_gpio(void)
279 imx_iomux_v3_setup_multiple_pads(gpio_pads
, ARRAY_SIZE(gpio_pads
));
282 iomux_v3_cfg_t
const usb_pads
[] = {
284 MX6_PAD_GPIO_0__GPIO1_IO00
| MUX_PAD_CTRL(NO_PAD_CTRL
),
285 # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
287 MX6_PAD_EIM_D28__GPIO3_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
),
288 # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
290 MX6_PAD_ENET_RX_ER__USB_OTG_ID
| MUX_PAD_CTRL(WEAK_PULLUP
),
292 MX6_PAD_EIM_D22__GPIO3_IO22
| MUX_PAD_CTRL(NO_PAD_CTRL
),
293 # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
297 * UARTs are used in DTE mode, switch the mode on all UARTs before
298 * any pinmuxing connects a (DCE) output to a transceiver output.
300 #define UFCR 0x90 /* FIFO Control Register */
301 #define UFCR_DCEDTE (1<<6) /* DCE=0 */
303 static void setup_dtemode_uart(void)
305 setbits_le32((u32
*)(UART1_BASE
+ UFCR
), UFCR_DCEDTE
);
306 setbits_le32((u32
*)(UART2_BASE
+ UFCR
), UFCR_DCEDTE
);
307 setbits_le32((u32
*)(UART4_BASE
+ UFCR
), UFCR_DCEDTE
);
308 setbits_le32((u32
*)(UART5_BASE
+ UFCR
), UFCR_DCEDTE
);
310 static void setup_dcemode_uart(void)
312 clrbits_le32((u32
*)(UART1_BASE
+ UFCR
), UFCR_DCEDTE
);
313 clrbits_le32((u32
*)(UART2_BASE
+ UFCR
), UFCR_DCEDTE
);
314 clrbits_le32((u32
*)(UART4_BASE
+ UFCR
), UFCR_DCEDTE
);
315 clrbits_le32((u32
*)(UART5_BASE
+ UFCR
), UFCR_DCEDTE
);
318 static void setup_iomux_dte_uart(void)
320 setup_dtemode_uart();
321 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte
,
322 ARRAY_SIZE(uart1_pads_dte
));
325 static void setup_iomux_dce_uart(void)
327 setup_dcemode_uart();
328 imx_iomux_v3_setup_multiple_pads(uart1_pads_dce
,
329 ARRAY_SIZE(uart1_pads_dce
));
332 #ifdef CONFIG_USB_EHCI_MX6
333 int board_ehci_hcd_init(int port
)
335 imx_iomux_v3_setup_multiple_pads(usb_pads
, ARRAY_SIZE(usb_pads
));
339 int board_ehci_power(int port
, int on
)
343 /* control OTG power */
344 gpio_direction_output(GPIO_USBO_EN
, on
);
348 /* Control MXM USBH */
349 gpio_direction_output(GPIO_USBH_EN
, on
);
351 /* Control onboard USB Hub VBUS */
352 gpio_direction_output(GPIO_USB_VBUS_DET
, on
);
362 #ifdef CONFIG_FSL_ESDHC
363 /* use the following sequence: eMMC, MMC, SD */
364 struct fsl_esdhc_cfg usdhc_cfg
[CONFIG_SYS_FSL_USDHC_NUM
] = {
370 int board_mmc_getcd(struct mmc
*mmc
)
372 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
373 int ret
= true; /* default: assume inserted */
375 switch (cfg
->esdhc_base
) {
376 case USDHC1_BASE_ADDR
:
377 gpio_direction_input(GPIO_MMC_CD
);
378 ret
= !gpio_get_value(GPIO_MMC_CD
);
380 case USDHC2_BASE_ADDR
:
381 gpio_direction_input(GPIO_SD_CD
);
382 ret
= !gpio_get_value(GPIO_SD_CD
);
389 int board_mmc_init(bd_t
*bis
)
391 #ifndef CONFIG_SPL_BUILD
395 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
396 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
397 usdhc_cfg
[2].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
399 usdhc_cfg
[0].max_bus_width
= 8;
400 usdhc_cfg
[1].max_bus_width
= 8;
401 usdhc_cfg
[2].max_bus_width
= 4;
403 for (index
= 0; index
< CONFIG_SYS_FSL_USDHC_NUM
; ++index
) {
406 imx_iomux_v3_setup_multiple_pads(
407 usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
410 imx_iomux_v3_setup_multiple_pads(
411 usdhc1_pads
, ARRAY_SIZE(usdhc1_pads
));
414 imx_iomux_v3_setup_multiple_pads(
415 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
418 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
419 index
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
423 status
|= fsl_esdhc_initialize(bis
, &usdhc_cfg
[index
]);
428 struct src
*psrc
= (struct src
*)SRC_BASE_ADDR
;
429 unsigned reg
= readl(&psrc
->sbmr1
) >> 11;
431 * Upon reading BOOT_CFG register the following map is done:
432 * Bit 11 and 12 of BOOT_CFG register can determine the current
441 imx_iomux_v3_setup_multiple_pads(
442 usdhc1_pads
, ARRAY_SIZE(usdhc1_pads
));
443 usdhc_cfg
[0].esdhc_base
= USDHC1_BASE_ADDR
;
444 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
445 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
448 imx_iomux_v3_setup_multiple_pads(
449 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
450 usdhc_cfg
[0].esdhc_base
= USDHC2_BASE_ADDR
;
451 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
452 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
455 imx_iomux_v3_setup_multiple_pads(
456 usdhc3_pads
, ARRAY_SIZE(usdhc3_pads
));
457 usdhc_cfg
[0].esdhc_base
= USDHC3_BASE_ADDR
;
458 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
459 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
462 puts("MMC boot device not available");
465 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
470 int board_phy_config(struct phy_device
*phydev
)
472 mx6_rgmii_rework(phydev
);
473 if (phydev
->drv
->config
)
474 phydev
->drv
->config(phydev
);
479 int board_eth_init(bd_t
*bis
)
481 uint32_t base
= IMX_FEC_BASE
;
482 struct mii_dev
*bus
= NULL
;
483 struct phy_device
*phydev
= NULL
;
488 #ifdef CONFIG_FEC_MXC
489 bus
= fec_get_miibus(base
, -1);
492 bus
->reset
= reset_enet_phy
;
493 /* scan PHY 4,5,6,7 */
494 phydev
= phy_find_by_mask(bus
, (0xf << 4), PHY_INTERFACE_MODE_RGMII
);
497 puts("no PHY found\n");
500 printf("using PHY at %d\n", phydev
->addr
);
501 ret
= fec_probe(bis
, -1, base
, bus
, phydev
);
503 printf("FEC MXC: %s:failed\n", __func__
);
511 static iomux_v3_cfg_t
const pwr_intb_pads
[] = {
513 * the bootrom sets the iomux to vselect, potentially connecting
514 * two outputs. Set this back to GPIO
516 MX6_PAD_GPIO_18__GPIO7_IO13
| MUX_PAD_CTRL(NO_PAD_CTRL
)
519 #if defined(CONFIG_VIDEO_IPUV3)
521 static iomux_v3_cfg_t
const backlight_pads
[] = {
522 /* Backlight on RGB connector: J15 */
523 MX6_PAD_EIM_DA13__GPIO3_IO13
| MUX_PAD_CTRL(NO_PAD_CTRL
),
524 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
525 /* additional CPU pin on BKL_PWM, keep in tristate */
526 MX6_PAD_EIM_DA14__GPIO3_IO14
| MUX_PAD_CTRL(TRISTATE
),
527 /* Backlight PWM, used as GPIO in U-Boot */
528 MX6_PAD_SD4_DAT2__GPIO2_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
),
529 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
530 /* buffer output enable 0: buffer enabled */
531 MX6_PAD_EIM_A25__GPIO5_IO02
| MUX_PAD_CTRL(WEAK_PULLUP
),
532 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
533 /* PSAVE# integrated VDAC */
534 MX6_PAD_EIM_BCLK__GPIO6_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
),
535 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
538 static iomux_v3_cfg_t
const rgb_pads
[] = {
539 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK
| MUX_PAD_CTRL(OUTPUT_RGB
),
540 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15
| MUX_PAD_CTRL(OUTPUT_RGB
),
541 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02
| MUX_PAD_CTRL(OUTPUT_RGB
),
542 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03
| MUX_PAD_CTRL(OUTPUT_RGB
),
543 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00
| MUX_PAD_CTRL(OUTPUT_RGB
),
544 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01
| MUX_PAD_CTRL(OUTPUT_RGB
),
545 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02
| MUX_PAD_CTRL(OUTPUT_RGB
),
546 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03
| MUX_PAD_CTRL(OUTPUT_RGB
),
547 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04
| MUX_PAD_CTRL(OUTPUT_RGB
),
548 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05
| MUX_PAD_CTRL(OUTPUT_RGB
),
549 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06
| MUX_PAD_CTRL(OUTPUT_RGB
),
550 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07
| MUX_PAD_CTRL(OUTPUT_RGB
),
551 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08
| MUX_PAD_CTRL(OUTPUT_RGB
),
552 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09
| MUX_PAD_CTRL(OUTPUT_RGB
),
553 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10
| MUX_PAD_CTRL(OUTPUT_RGB
),
554 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11
| MUX_PAD_CTRL(OUTPUT_RGB
),
555 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12
| MUX_PAD_CTRL(OUTPUT_RGB
),
556 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13
| MUX_PAD_CTRL(OUTPUT_RGB
),
557 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14
| MUX_PAD_CTRL(OUTPUT_RGB
),
558 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15
| MUX_PAD_CTRL(OUTPUT_RGB
),
559 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16
| MUX_PAD_CTRL(OUTPUT_RGB
),
560 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17
| MUX_PAD_CTRL(OUTPUT_RGB
),
561 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18
| MUX_PAD_CTRL(OUTPUT_RGB
),
562 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19
| MUX_PAD_CTRL(OUTPUT_RGB
),
563 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22
| MUX_PAD_CTRL(OUTPUT_RGB
),
564 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23
| MUX_PAD_CTRL(OUTPUT_RGB
),
565 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21
| MUX_PAD_CTRL(OUTPUT_RGB
),
566 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20
| MUX_PAD_CTRL(OUTPUT_RGB
),
569 static void do_enable_hdmi(struct display_info_t
const *dev
)
571 imx_enable_hdmi_phy();
574 static int detect_i2c(struct display_info_t
const *dev
)
576 return (0 == i2c_set_bus_num(dev
->bus
)) &&
577 (0 == i2c_probe(dev
->addr
));
580 static void enable_lvds(struct display_info_t
const *dev
)
582 struct iomuxc
*iomux
= (struct iomuxc
*)
584 u32 reg
= readl(&iomux
->gpr
[2]);
585 reg
|= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
;
586 writel(reg
, &iomux
->gpr
[2]);
587 gpio_direction_output(RGB_BACKLIGHT_GP
, 1);
588 gpio_direction_output(RGB_BACKLIGHTPWM_GP
, 0);
589 gpio_direction_output(RGB_BACKLIGHTPWM_OE
, 0);
592 static void enable_rgb(struct display_info_t
const *dev
)
594 imx_iomux_v3_setup_multiple_pads(
596 ARRAY_SIZE(rgb_pads
));
597 gpio_direction_output(RGB_BACKLIGHT_GP
, 1);
598 gpio_direction_output(RGB_BACKLIGHTPWM_GP
, 0);
599 gpio_direction_output(RGB_BACKLIGHTPWM_OE
, 0);
602 static int detect_default(struct display_info_t
const *dev
)
608 struct display_info_t
const displays
[] = {{
611 .pixfmt
= IPU_PIX_FMT_RGB24
,
612 .detect
= detect_hdmi
,
613 .enable
= do_enable_hdmi
,
627 .vmode
= FB_VMODE_NONINTERLACED
632 .pixfmt
= IPU_PIX_FMT_RGB24
,
633 .detect
= detect_default
,
634 .enable
= enable_rgb
,
648 .vmode
= FB_VMODE_NONINTERLACED
653 .pixfmt
= IPU_PIX_FMT_RGB24
,
654 .enable
= enable_rgb
,
668 .vmode
= FB_VMODE_NONINTERLACED
672 .pixfmt
= IPU_PIX_FMT_LVDS666
,
673 .detect
= detect_i2c
,
674 .enable
= enable_lvds
,
676 .name
= "wsvga-lvds",
688 .vmode
= FB_VMODE_NONINTERLACED
690 size_t display_count
= ARRAY_SIZE(displays
);
692 static void setup_display(void)
694 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
695 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
700 /* Turn on LDB0,IPU,IPU DI0 clocks */
701 reg
= __raw_readl(&mxc_ccm
->CCGR3
);
702 reg
|= MXC_CCM_CCGR3_LDB_DI0_MASK
;
703 writel(reg
, &mxc_ccm
->CCGR3
);
705 /* set LDB0, LDB1 clk select to 011/011 */
706 reg
= readl(&mxc_ccm
->cs2cdr
);
707 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
708 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
709 reg
|= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
)
710 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
711 writel(reg
, &mxc_ccm
->cs2cdr
);
713 reg
= readl(&mxc_ccm
->cscmr2
);
714 reg
|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
;
715 writel(reg
, &mxc_ccm
->cscmr2
);
717 reg
= readl(&mxc_ccm
->chsccdr
);
718 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
719 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
720 writel(reg
, &mxc_ccm
->chsccdr
);
722 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
723 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
724 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
725 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
726 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
727 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
728 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
729 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
730 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
;
731 writel(reg
, &iomux
->gpr
[2]);
733 reg
= readl(&iomux
->gpr
[3]);
734 reg
= (reg
& ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
735 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK
))
736 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
737 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET
);
738 writel(reg
, &iomux
->gpr
[3]);
740 /* backlight unconditionally on for now */
741 imx_iomux_v3_setup_multiple_pads(backlight_pads
,
742 ARRAY_SIZE(backlight_pads
));
743 /* use 0 for EDT 7", use 1 for LG fullHD panel */
744 gpio_direction_output(RGB_BACKLIGHTPWM_GP
, 0);
745 gpio_direction_output(RGB_BACKLIGHTPWM_OE
, 0);
746 gpio_direction_output(RGB_BACKLIGHT_GP
, 1);
748 #endif /* defined(CONFIG_VIDEO_IPUV3) */
750 int board_early_init_f(void)
752 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads
,
753 ARRAY_SIZE(pwr_intb_pads
));
754 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
755 setup_iomux_dte_uart();
757 setup_iomux_dce_uart();
760 #if defined(CONFIG_VIDEO_IPUV3)
767 * Do not overwrite the console
768 * Use always serial for U-Boot console
770 int overwrite_console(void)
777 /* address of boot parameters */
778 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
780 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
781 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info_loc
);
782 setup_i2c(2, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info3
);
784 #ifdef CONFIG_TDX_CMD_IMX_MFGR
797 #ifdef CONFIG_BOARD_LATE_INIT
798 int board_late_init(void)
800 #if defined(CONFIG_REVISION_TAG) && \
801 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
805 rev
= get_board_rev();
806 snprintf(env_str
, ARRAY_SIZE(env_str
), "%.4x", rev
);
807 env_set("board_rev", env_str
);
809 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
810 if ((rev
& 0xfff0) == 0x0100) {
813 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
814 setup_iomux_dce_uart();
816 /* if using the default device tree, use version for V1.0 HW */
817 fdt_env
= getenv("fdt_file");
818 if ((fdt_env
!= NULL
) && (strcmp(FDT_FILE
, fdt_env
) == 0)) {
819 env_set("fdt_file", FDT_FILE_V1_0
);
820 printf("patching fdt_file to " FDT_FILE_V1_0
"\n");
821 #ifndef CONFIG_ENV_IS_NOWHERE
826 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
827 #endif /* CONFIG_REVISION_TAG */
831 #endif /* CONFIG_BOARD_LATE_INIT */
833 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
834 int ft_system_setup(void *blob
, bd_t
*bd
)
845 switch (get_cpu_temp_grade(&minc
, &maxc
)) {
846 case TEMP_AUTOMOTIVE
:
847 case TEMP_INDUSTRIAL
:
849 case TEMP_EXTCOMMERCIAL
:
853 printf("Model: Toradex Apalis iMX6 %s %s%s\n",
854 is_cpu_type(MXC_CPU_MX6D
) ? "Dual" : "Quad",
855 (gd
->ram_size
== 0x80000000) ? "2GB" :
856 (gd
->ram_size
== 0x40000000) ? "1GB" : "512MB", it
);
860 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
861 int ft_board_setup(void *blob
, bd_t
*bd
)
863 return ft_common_board_setup(blob
, bd
);
867 #ifdef CONFIG_CMD_BMODE
868 static const struct boot_mode board_boot_modes
[] = {
869 /* 4-bit bus width */
870 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
871 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
876 int misc_init_r(void)
878 #ifdef CONFIG_CMD_BMODE
879 add_board_boot_modes(board_boot_modes
);
884 #ifdef CONFIG_LDO_BYPASS_CHECK
885 /* TODO, use external pmic, for now always ldo_enable */
886 void ldo_mode_set(int ldo_bypass
)
892 #ifdef CONFIG_SPL_BUILD
895 #include "asm/arch/mx6q-ddr.h"
896 #include "asm/arch/iomux.h"
897 #include "asm/arch/crm_regs.h"
899 static int mx6_com_dcd_table
[] = {
901 MX6_IOM_DRAM_SDQS0
, 0x00000030,
902 MX6_IOM_DRAM_SDQS1
, 0x00000030,
903 MX6_IOM_DRAM_SDQS2
, 0x00000030,
904 MX6_IOM_DRAM_SDQS3
, 0x00000030,
905 MX6_IOM_DRAM_SDQS4
, 0x00000030,
906 MX6_IOM_DRAM_SDQS5
, 0x00000030,
907 MX6_IOM_DRAM_SDQS6
, 0x00000030,
908 MX6_IOM_DRAM_SDQS7
, 0x00000030,
910 MX6_IOM_GRP_B0DS
, 0x00000030,
911 MX6_IOM_GRP_B1DS
, 0x00000030,
912 MX6_IOM_GRP_B2DS
, 0x00000030,
913 MX6_IOM_GRP_B3DS
, 0x00000030,
914 MX6_IOM_GRP_B4DS
, 0x00000030,
915 MX6_IOM_GRP_B5DS
, 0x00000030,
916 MX6_IOM_GRP_B6DS
, 0x00000030,
917 MX6_IOM_GRP_B7DS
, 0x00000030,
918 MX6_IOM_GRP_ADDDS
, 0x00000030,
919 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
920 MX6_IOM_GRP_CTLDS
, 0x00000030,
922 MX6_IOM_DRAM_DQM0
, 0x00020030,
923 MX6_IOM_DRAM_DQM1
, 0x00020030,
924 MX6_IOM_DRAM_DQM2
, 0x00020030,
925 MX6_IOM_DRAM_DQM3
, 0x00020030,
926 MX6_IOM_DRAM_DQM4
, 0x00020030,
927 MX6_IOM_DRAM_DQM5
, 0x00020030,
928 MX6_IOM_DRAM_DQM6
, 0x00020030,
929 MX6_IOM_DRAM_DQM7
, 0x00020030,
931 MX6_IOM_DRAM_CAS
, 0x00020030,
932 MX6_IOM_DRAM_RAS
, 0x00020030,
933 MX6_IOM_DRAM_SDCLK_0
, 0x00020030,
934 MX6_IOM_DRAM_SDCLK_1
, 0x00020030,
936 MX6_IOM_DRAM_RESET
, 0x00020030,
937 MX6_IOM_DRAM_SDCKE0
, 0x00003000,
938 MX6_IOM_DRAM_SDCKE1
, 0x00003000,
940 MX6_IOM_DRAM_SDODT0
, 0x00003030,
941 MX6_IOM_DRAM_SDODT1
, 0x00003030,
943 /* (differential input) */
944 MX6_IOM_DDRMODE_CTL
, 0x00020000,
945 /* (differential input) */
946 MX6_IOM_GRP_DDRMODE
, 0x00020000,
947 /* disable ddr pullups */
948 MX6_IOM_GRP_DDRPKE
, 0x00000000,
949 MX6_IOM_DRAM_SDBA2
, 0x00000000,
950 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
951 MX6_IOM_GRP_DDR_TYPE
, 0x000C0000,
953 /* Read data DQ Byte0-3 delay */
954 MX6_MMDC_P0_MPRDDQBY0DL
, 0x33333333,
955 MX6_MMDC_P0_MPRDDQBY1DL
, 0x33333333,
956 MX6_MMDC_P0_MPRDDQBY2DL
, 0x33333333,
957 MX6_MMDC_P0_MPRDDQBY3DL
, 0x33333333,
958 MX6_MMDC_P1_MPRDDQBY0DL
, 0x33333333,
959 MX6_MMDC_P1_MPRDDQBY1DL
, 0x33333333,
960 MX6_MMDC_P1_MPRDDQBY2DL
, 0x33333333,
961 MX6_MMDC_P1_MPRDDQBY3DL
, 0x33333333,
964 * MDMISC mirroring interleaved (row/bank/col)
966 MX6_MMDC_P0_MDMISC
, 0x00081740,
971 MX6_MMDC_P0_MDSCR
, 0x00008000,
973 /* 1066mhz_4x128mx16.cfg */
975 MX6_MMDC_P0_MDPDC
, 0x00020036,
976 MX6_MMDC_P0_MDCFG0
, 0x555A7954,
977 MX6_MMDC_P0_MDCFG1
, 0xDB328F64,
978 MX6_MMDC_P0_MDCFG2
, 0x01FF00DB,
979 MX6_MMDC_P0_MDRWD
, 0x000026D2,
980 MX6_MMDC_P0_MDOR
, 0x005A1023,
981 MX6_MMDC_P0_MDOTC
, 0x09555050,
982 MX6_MMDC_P0_MDPDC
, 0x00025576,
983 MX6_MMDC_P0_MDASP
, 0x00000027,
984 MX6_MMDC_P0_MDCTL
, 0x831A0000,
985 MX6_MMDC_P0_MDSCR
, 0x04088032,
986 MX6_MMDC_P0_MDSCR
, 0x00008033,
987 MX6_MMDC_P0_MDSCR
, 0x00428031,
988 MX6_MMDC_P0_MDSCR
, 0x19308030,
989 MX6_MMDC_P0_MDSCR
, 0x04008040,
990 MX6_MMDC_P0_MPZQHWCTRL
, 0xA1390003,
991 MX6_MMDC_P1_MPZQHWCTRL
, 0xA1390003,
992 MX6_MMDC_P0_MDREF
, 0x00005800,
993 MX6_MMDC_P0_MPODTCTRL
, 0x00000000,
994 MX6_MMDC_P1_MPODTCTRL
, 0x00000000,
996 MX6_MMDC_P0_MPDGCTRL0
, 0x432A0338,
997 MX6_MMDC_P0_MPDGCTRL1
, 0x03260324,
998 MX6_MMDC_P1_MPDGCTRL0
, 0x43340344,
999 MX6_MMDC_P1_MPDGCTRL1
, 0x031E027C,
1001 MX6_MMDC_P0_MPRDDLCTL
, 0x33272D2E,
1002 MX6_MMDC_P1_MPRDDLCTL
, 0x2F312B37,
1004 MX6_MMDC_P0_MPWRDLCTL
, 0x3A35433C,
1005 MX6_MMDC_P1_MPWRDLCTL
, 0x4336453F,
1007 MX6_MMDC_P0_MPWLDECTRL0
, 0x0009000E,
1008 MX6_MMDC_P0_MPWLDECTRL1
, 0x0018000B,
1009 MX6_MMDC_P1_MPWLDECTRL0
, 0x00060015,
1010 MX6_MMDC_P1_MPWLDECTRL1
, 0x0006000E,
1012 MX6_MMDC_P0_MPMUR0
, 0x00000800,
1013 MX6_MMDC_P1_MPMUR0
, 0x00000800,
1014 MX6_MMDC_P0_MDSCR
, 0x00000000,
1015 MX6_MMDC_P0_MAPSR
, 0x00011006,
1018 static int mx6_it_dcd_table
[] = {
1020 MX6_IOM_DRAM_SDQS0
, 0x00000030,
1021 MX6_IOM_DRAM_SDQS1
, 0x00000030,
1022 MX6_IOM_DRAM_SDQS2
, 0x00000030,
1023 MX6_IOM_DRAM_SDQS3
, 0x00000030,
1024 MX6_IOM_DRAM_SDQS4
, 0x00000030,
1025 MX6_IOM_DRAM_SDQS5
, 0x00000030,
1026 MX6_IOM_DRAM_SDQS6
, 0x00000030,
1027 MX6_IOM_DRAM_SDQS7
, 0x00000030,
1029 MX6_IOM_GRP_B0DS
, 0x00000030,
1030 MX6_IOM_GRP_B1DS
, 0x00000030,
1031 MX6_IOM_GRP_B2DS
, 0x00000030,
1032 MX6_IOM_GRP_B3DS
, 0x00000030,
1033 MX6_IOM_GRP_B4DS
, 0x00000030,
1034 MX6_IOM_GRP_B5DS
, 0x00000030,
1035 MX6_IOM_GRP_B6DS
, 0x00000030,
1036 MX6_IOM_GRP_B7DS
, 0x00000030,
1037 MX6_IOM_GRP_ADDDS
, 0x00000030,
1038 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1039 MX6_IOM_GRP_CTLDS
, 0x00000030,
1041 MX6_IOM_DRAM_DQM0
, 0x00020030,
1042 MX6_IOM_DRAM_DQM1
, 0x00020030,
1043 MX6_IOM_DRAM_DQM2
, 0x00020030,
1044 MX6_IOM_DRAM_DQM3
, 0x00020030,
1045 MX6_IOM_DRAM_DQM4
, 0x00020030,
1046 MX6_IOM_DRAM_DQM5
, 0x00020030,
1047 MX6_IOM_DRAM_DQM6
, 0x00020030,
1048 MX6_IOM_DRAM_DQM7
, 0x00020030,
1050 MX6_IOM_DRAM_CAS
, 0x00020030,
1051 MX6_IOM_DRAM_RAS
, 0x00020030,
1052 MX6_IOM_DRAM_SDCLK_0
, 0x00020030,
1053 MX6_IOM_DRAM_SDCLK_1
, 0x00020030,
1055 MX6_IOM_DRAM_RESET
, 0x00020030,
1056 MX6_IOM_DRAM_SDCKE0
, 0x00003000,
1057 MX6_IOM_DRAM_SDCKE1
, 0x00003000,
1059 MX6_IOM_DRAM_SDODT0
, 0x00003030,
1060 MX6_IOM_DRAM_SDODT1
, 0x00003030,
1062 /* (differential input) */
1063 MX6_IOM_DDRMODE_CTL
, 0x00020000,
1064 /* (differential input) */
1065 MX6_IOM_GRP_DDRMODE
, 0x00020000,
1066 /* disable ddr pullups */
1067 MX6_IOM_GRP_DDRPKE
, 0x00000000,
1068 MX6_IOM_DRAM_SDBA2
, 0x00000000,
1069 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1070 MX6_IOM_GRP_DDR_TYPE
, 0x000C0000,
1072 /* Read data DQ Byte0-3 delay */
1073 MX6_MMDC_P0_MPRDDQBY0DL
, 0x33333333,
1074 MX6_MMDC_P0_MPRDDQBY1DL
, 0x33333333,
1075 MX6_MMDC_P0_MPRDDQBY2DL
, 0x33333333,
1076 MX6_MMDC_P0_MPRDDQBY3DL
, 0x33333333,
1077 MX6_MMDC_P1_MPRDDQBY0DL
, 0x33333333,
1078 MX6_MMDC_P1_MPRDDQBY1DL
, 0x33333333,
1079 MX6_MMDC_P1_MPRDDQBY2DL
, 0x33333333,
1080 MX6_MMDC_P1_MPRDDQBY3DL
, 0x33333333,
1083 * MDMISC mirroring interleaved (row/bank/col)
1085 MX6_MMDC_P0_MDMISC
, 0x00081740,
1090 MX6_MMDC_P0_MDSCR
, 0x00008000,
1092 /* 1066mhz_4x256mx16.cfg */
1094 MX6_MMDC_P0_MDPDC
, 0x00020036,
1095 MX6_MMDC_P0_MDCFG0
, 0x898E78f5,
1096 MX6_MMDC_P0_MDCFG1
, 0xff328f64,
1097 MX6_MMDC_P0_MDCFG2
, 0x01FF00DB,
1098 MX6_MMDC_P0_MDRWD
, 0x000026D2,
1099 MX6_MMDC_P0_MDOR
, 0x008E1023,
1100 MX6_MMDC_P0_MDOTC
, 0x09444040,
1101 MX6_MMDC_P0_MDPDC
, 0x00025576,
1102 MX6_MMDC_P0_MDASP
, 0x00000047,
1103 MX6_MMDC_P0_MDCTL
, 0x841A0000,
1104 MX6_MMDC_P0_MDSCR
, 0x02888032,
1105 MX6_MMDC_P0_MDSCR
, 0x00008033,
1106 MX6_MMDC_P0_MDSCR
, 0x00048031,
1107 MX6_MMDC_P0_MDSCR
, 0x19408030,
1108 MX6_MMDC_P0_MDSCR
, 0x04008040,
1109 MX6_MMDC_P0_MPZQHWCTRL
, 0xA1390003,
1110 MX6_MMDC_P1_MPZQHWCTRL
, 0xA1390003,
1111 MX6_MMDC_P0_MDREF
, 0x00007800,
1112 MX6_MMDC_P0_MPODTCTRL
, 0x00022227,
1113 MX6_MMDC_P1_MPODTCTRL
, 0x00022227,
1115 MX6_MMDC_P0_MPDGCTRL0
, 0x03300338,
1116 MX6_MMDC_P0_MPDGCTRL1
, 0x03240324,
1117 MX6_MMDC_P1_MPDGCTRL0
, 0x03440350,
1118 MX6_MMDC_P1_MPDGCTRL1
, 0x032C0308,
1120 MX6_MMDC_P0_MPRDDLCTL
, 0x40363C3E,
1121 MX6_MMDC_P1_MPRDDLCTL
, 0x3C3E3C46,
1123 MX6_MMDC_P0_MPWRDLCTL
, 0x403E463E,
1124 MX6_MMDC_P1_MPWRDLCTL
, 0x4A384C46,
1126 MX6_MMDC_P0_MPWLDECTRL0
, 0x0009000E,
1127 MX6_MMDC_P0_MPWLDECTRL1
, 0x0018000B,
1128 MX6_MMDC_P1_MPWLDECTRL0
, 0x00060015,
1129 MX6_MMDC_P1_MPWLDECTRL1
, 0x0006000E,
1131 MX6_MMDC_P0_MPMUR0
, 0x00000800,
1132 MX6_MMDC_P1_MPMUR0
, 0x00000800,
1133 MX6_MMDC_P0_MDSCR
, 0x00000000,
1134 MX6_MMDC_P0_MAPSR
, 0x00011006,
1138 static void ccgr_init(void)
1140 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1142 writel(0x00C03F3F, &ccm
->CCGR0
);
1143 writel(0x0030FC03, &ccm
->CCGR1
);
1144 writel(0x0FFFFFF3, &ccm
->CCGR2
);
1145 writel(0x3FF0300F, &ccm
->CCGR3
);
1146 writel(0x00FFF300, &ccm
->CCGR4
);
1147 writel(0x0F0000F3, &ccm
->CCGR5
);
1148 writel(0x000003FF, &ccm
->CCGR6
);
1151 * Setup CCM_CCOSR register as follows:
1153 * cko1_en = 1 --> CKO1 enabled
1154 * cko1_div = 111 --> divide by 8
1155 * cko1_sel = 1011 --> ahb_clk_root
1157 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1159 writel(0x000000FB, &ccm
->ccosr
);
1162 static void gpr_init(void)
1164 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
1166 /* enable AXI cache for VDOA/VPU/IPU */
1167 writel(0xF00000CF, &iomux
->gpr
[4]);
1168 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
1169 writel(0x007F007F, &iomux
->gpr
[6]);
1170 writel(0x007F007F, &iomux
->gpr
[7]);
1173 static void ddr_init(int *table
, int size
)
1177 for (i
= 0; i
< size
/ 2 ; i
++)
1178 writel(table
[2 * i
+ 1], table
[2 * i
]);
1181 static void spl_dram_init(void)
1185 switch (get_cpu_temp_grade(&minc
, &maxc
)) {
1186 case TEMP_COMMERCIAL
:
1187 case TEMP_EXTCOMMERCIAL
:
1188 puts("Commercial temperature grade DDR3 timings.\n");
1189 ddr_init(mx6_com_dcd_table
, ARRAY_SIZE(mx6_com_dcd_table
));
1191 case TEMP_INDUSTRIAL
:
1192 case TEMP_AUTOMOTIVE
:
1194 puts("Industrial temperature grade DDR3 timings.\n");
1195 ddr_init(mx6_it_dcd_table
, ARRAY_SIZE(mx6_it_dcd_table
));
1201 void board_init_f(ulong dummy
)
1203 /* setup AIPS and disable watchdog */
1209 /* iomux and setup of i2c */
1210 board_early_init_f();
1212 /* setup GP timer */
1215 /* UART clocks enabled and gd valid - init serial console */
1216 preloader_console_init();
1218 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1219 /* Make sure we use dte mode */
1220 setup_dtemode_uart();
1223 /* DDR initialization */
1226 /* Clear the BSS. */
1227 memset(__bss_start
, 0, __bss_end
- __bss_start
);
1229 /* load/boot image from boot device */
1230 board_init_r(NULL
, 0);
1233 void reset_cpu(ulong addr
)
1239 static struct mxc_serial_platdata mxc_serial_plat
= {
1240 .reg
= (struct mxc_uart
*)UART1_BASE
,
1244 U_BOOT_DEVICE(mxc_serial
) = {
1245 .name
= "serial_mxc",
1246 .platdata
= &mxc_serial_plat
,