board/total5200/total5200.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc5xxx.h>
  13 #include <pci.h>
  14 #include <netdev.h>
  15
  16 #include "sdram.h"
  17
  18 #if CONFIG_TOTAL5200_REV==2
  19 #include "mt48lc32m16a2-75.h"
  20 #else
  21 #include "mt48lc16m16a2-75.h"
  22 #endif
  23
  24 phys_size_t initdram (int board_type)
  25 {
  26         sdram_conf_t sdram_conf;
  27
  28         sdram_conf.ddr = SDRAM_DDR;
  29         sdram_conf.mode = SDRAM_MODE;
  30         sdram_conf.emode = 0;
  31         sdram_conf.control = SDRAM_CONTROL;
  32         sdram_conf.config1 = SDRAM_CONFIG1;
  33         sdram_conf.config2 = SDRAM_CONFIG2;
  34         sdram_conf.tapdelay = 0;
  35         return mpc5xxx_sdram_init (&sdram_conf);
  36 }
  37
  38 int checkboard (void)
  39 {
  40 #if CONFIG_TOTAL5200_REV==2
  41         puts ("Board: Total5200 Rev.2 ");
  42 #else
  43         puts ("Board: Total5200 ");
  44 #endif
  45
  46         /*
  47          * Retrieve FPGA Revision.
  48          */
  49         printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
  50
  51         /*
  52          * Take all peripherals in power-up mode.
  53          */
  54 #if CONFIG_TOTAL5200_REV==2
  55         *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
  56 #else
  57         *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
  58 #endif
  59
  60         return 0;
  61 }
  62
  63 #ifdef  CONFIG_PCI
  64 static struct pci_controller hose;
  65
  66 extern void pci_mpc5xxx_init(struct pci_controller *);
  67
  68 void pci_init_board(void)
  69 {
  70         pci_mpc5xxx_init(&hose);
  71 }
  72 #endif
  73
  74 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
  75
  76 /* IRDA_1 aka PSC6_3 (pin C13) */
  77 #define GPIO_IRDA_1     0x20000000UL
  78
  79 void init_ide_reset (void)
  80 {
  81         debug ("init_ide_reset\n");
  82
  83         /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
  84         *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
  85         *(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
  86 }
  87
  88 void ide_set_reset (int idereset)
  89 {
  90         debug ("ide_reset(%d)\n", idereset);
  91
  92         if (idereset) {
  93                 *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
  94         } else {
  95                 *(vu_long *) MPC5XXX_GPIO_DATA_O |=  GPIO_IRDA_1;
  96         }
  97 }
  98 #endif
  99
 100 #ifdef CONFIG_VIDEO_SED13806
 101 #include <sed13806.h>
 102
 103 #define DISPLAY_WIDTH   640
 104 #define DISPLAY_HEIGHT  480
 105
 106 #ifdef CONFIG_VIDEO_SED13806_8BPP
 107 #error CONFIG_VIDEO_SED13806_8BPP not supported.
 108 #endif /* CONFIG_VIDEO_SED13806_8BPP */
 109
 110 #ifdef CONFIG_VIDEO_SED13806_16BPP
 111 static const S1D_REGS init_regs [] =
 112 {
 113     {0x0001,0x00},   /* Miscellaneous Register */
 114     {0x01FC,0x00},   /* Display Mode Register */
 115     {0x0004,0x00},   /* General IO Pins Configuration Register 0 */
 116     {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
 117     {0x0008,0x00},   /* General IO Pins Control Register 0 */
 118     {0x0009,0x00},   /* General IO Pins Control Register 1 */
 119     {0x0010,0x02},   /* Memory Clock Configuration Register */
 120     {0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
 121     {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
 122     {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
 123     {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
 124     {0x0021,0x03},   /* DRAM Refresh Rate Register */
 125     {0x002A,0x00},   /* DRAM Timings Control Register 0 */
 126     {0x002B,0x01},   /* DRAM Timings Control Register 1 */
 127     {0x0020,0x80},   /* Memory Configuration Register */
 128     {0x0030,0x25},   /* Panel Type Register */
 129     {0x0031,0x00},   /* MOD Rate Register */
 130     {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
 131     {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
 132     {0x0035,0x01},   /* TFT FPLINE Start Position Register */
 133     {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
 134     {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
 135     {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
 136     {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
 137     {0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
 138     {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
 139     {0x0040,0x05},   /* LCD Display Mode Register */
 140     {0x0041,0x00},   /* LCD Miscellaneous Register */
 141     {0x0042,0x00},   /* LCD Display Start Address Register 0 */
 142     {0x0043,0x00},   /* LCD Display Start Address Register 1 */
 143     {0x0044,0x00},   /* LCD Display Start Address Register 2 */
 144     {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
 145     {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
 146     {0x0048,0x00},   /* LCD Pixel Panning Register */
 147     {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
 148     {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
 149     {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
 150     {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
 151     {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
 152     {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
 153     {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
 154     {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
 155     {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
 156     {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
 157     {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
 158     {0x005B,0x10},   /* TV Output Control Register */
 159     {0x0060,0x05},   /* CRT/TV Display Mode Register */
 160     {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
 161     {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
 162     {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
 163     {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
 164     {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
 165     {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
 166     {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
 167     {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
 168     {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
 169     {0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
 170     {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
 171     {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
 172     {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
 173     {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
 174     {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
 175     {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
 176     {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
 177     {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
 178     {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
 179     {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
 180     {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
 181     {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
 182     {0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
 183     {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
 184     {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
 185     {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
 186     {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
 187     {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
 188     {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
 189     {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
 190     {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
 191     {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
 192     {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
 193     {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
 194     {0x0100,0x00},   /* BitBlt Control Register 0 */
 195     {0x0101,0x00},   /* BitBlt Control Register 1 */
 196     {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
 197     {0x0103,0x00},   /* BitBlt Operation Register */
 198     {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
 199     {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
 200     {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
 201     {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
 202     {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
 203     {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
 204     {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
 205     {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
 206     {0x0110,0x00},   /* BitBlt Width Register 0 */
 207     {0x0111,0x00},   /* BitBlt Width Register 1 */
 208     {0x0112,0x00},   /* BitBlt Height Register 0 */
 209     {0x0113,0x00},   /* BitBlt Height Register 1 */
 210     {0x0114,0x00},   /* BitBlt Background Color Register 0 */
 211     {0x0115,0x00},   /* BitBlt Background Color Register 1 */
 212     {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
 213     {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
 214     {0x01E0,0x00},   /* Look-Up Table Mode Register */
 215     {0x01E2,0x00},   /* Look-Up Table Address Register */
 216     {0x01E4,0x00},   /* Look-Up Table Data Register */
 217     {0x01F0,0x00},   /* Power Save Configuration Register */
 218     {0x01F1,0x00},   /* Power Save Status Register */
 219     {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
 220     {0x01FC,0x01},   /* Display Mode Register */
 221     {0, 0}
 222 };
 223 #endif /* CONFIG_VIDEO_SED13806_16BPP */
 224
 225 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 226 /* Return text to be printed besides the logo. */
 227 void video_get_info_str (int line_number, char *info)
 228 {
 229         if (line_number == 1) {
 230 #if CONFIG_TOTAL5200_REV==1
 231                 strcpy (info, " Total5200");
 232 #elif CONFIG_TOTAL5200_REV==2
 233                 strcpy (info, " Total5200 Rev.2");
 234 #else
 235 #error CONFIG_TOTAL5200_REV must be 1 or 2.
 236 #endif
 237         } else {
 238                 info [0] = '\0';
 239         }
 240 }
 241 #endif
 242
 243 /* Returns  SED13806 base address. First thing called in the driver. */
 244 unsigned int board_video_init (void)
 245 {
 246         return CONFIG_SYS_LCD_BASE;
 247 }
 248
 249 /* Called after initializing the SED13806 and before clearing the screen. */
 250 void board_validate_screen (unsigned int base)
 251 {
 252 }
 253
 254 /* Return a pointer to the initialization sequence. */
 255 const S1D_REGS *board_get_regs (void)
 256 {
 257         return init_regs;
 258 }
 259
 260 int board_get_width (void)
 261 {
 262         return DISPLAY_WIDTH;
 263 }
 264
 265 int board_get_height (void)
 266 {
 267         return DISPLAY_HEIGHT;
 268 }
 269
 270 #endif /* CONFIG_VIDEO_SED13806 */
 271
 272 int board_eth_init(bd_t *bis)
 273 {
 274         cpu_eth_init(bis); /* Built in FEC comes first */
 275         return pci_eth_init(bis);
 276 }