board/tqc/tqm85xx/law.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/fsl_law.h>
  28 #include <asm/mmu.h>
  29
  30 /*
  31  * LAW(Local Access Window) configuration:
  32  *
  33  * Standard mapping:
  34  *
  35  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  36  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  37  * 0xc000_0000     0xdfff_ffff     RapidIO or PCI express  512M
  38  * 0xe000_0000     0xe000_ffff     CCSR                    1M
  39  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
  40  * 0xe300_0000     0xe3ff_ffff     CAN and NAND Flash      16M
  41  * 0xef00_0000     0xefff_ffff     PCI express IO          16M
  42  * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       128M
  43  *
  44  * Big FLASH mapping:
  45  *
  46  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  47  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  48  * 0xa000_0000     0xa000_ffff     CCSR                    1M
  49  * 0xa200_0000     0xa2ff_ffff     PCI1 IO                 16M
  50  * 0xa300_0000     0xa3ff_ffff     CAN and NAND Flash      16M
  51  * 0xaf00_0000     0xafff_ffff     PCI express IO          16M
  52  * 0xb000_0000     0xbfff_ffff     RapidIO or PCI express  256M
  53  * 0xc000_0000     0xffff_ffff     FLASH (boot bank)       1G
  54  *
  55  * Notes:
  56  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  57  *    If flash is 8M at default position (last 8M), no LAW needed.
  58  */
  59
  60 #ifdef CONFIG_TQM_BIGFLASH
  61 #define LAW_3_SIZE LAW_SIZE_1G
  62 #define LAW_5_SIZE LAW_SIZE_256M
  63 #else
  64 #define LAW_3_SIZE LAW_SIZE_128M
  65 #define LAW_5_SIZE LAW_SIZE_512M
  66 #endif
  67
  68 struct law_entry law_table[] = {
  69         SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
  70         SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
  71         SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
  72         SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
  73 #ifdef CONFIG_PCIE1
  74         SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
  75 #else /* !CONFIG_PCIE1 */
  76         SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
  77 #endif /* CONFIG_PCIE1 */
  78 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
  79         SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
  80 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
  81 #ifdef CONFIG_PCIE1
  82         SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
  83 #endif /* CONFIG_PCIE */
  84 };
  85
  86 int num_law_entries = ARRAY_SIZE (law_table);