3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/mx5x_pins.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/iomux.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
41 DECLARE_GLOBAL_DATA_PTR
;
43 static u32 system_rev
;
45 #ifdef CONFIG_HW_WATCHDOG
48 void hw_watchdog_reset(void)
52 /* toggle watchdog trigger pin */
53 val
= mxc_gpio_get(66);
55 mxc_gpio_set(66, val
);
59 static void init_drive_strength(void)
61 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR
, PAD_CTL_DDR_INPUT_CMOS
);
62 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR
, PAD_CTL_PKE_ENABLE
);
63 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS
, PAD_CTL_PUE_KEEPER
);
64 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS
, PAD_CTL_100K_PU
);
65 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1
, PAD_CTL_SRE_FAST
);
66 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0
, PAD_CTL_DRV_HIGH
);
67 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1
, PAD_CTL_DRV_HIGH
);
68 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS
,
69 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
70 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS
,
71 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
72 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR
, PAD_CTL_PKE_ENABLE
);
73 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS
, PAD_CTL_PUE_KEEPER
);
74 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0
, PAD_CTL_HYS_NONE
);
75 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1
, PAD_CTL_HYS_NONE
);
76 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2
, PAD_CTL_HYS_NONE
);
77 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3
, PAD_CTL_HYS_NONE
);
78 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0
, PAD_CTL_SRE_FAST
);
79 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1
, PAD_CTL_SRE_FAST
);
80 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2
, PAD_CTL_SRE_FAST
);
81 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4
, PAD_CTL_SRE_FAST
);
82 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS
, PAD_CTL_100K_PU
);
83 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1
, PAD_CTL_DDR_INPUT_CMOS
);
84 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0
, PAD_CTL_DRV_MEDIUM
);
85 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1
, PAD_CTL_DRV_MEDIUM
);
86 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2
, PAD_CTL_DRV_MEDIUM
);
87 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4
, PAD_CTL_DRV_MEDIUM
);
89 /* Setting pad options */
90 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE
,
91 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
92 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
93 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0
,
94 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
95 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
96 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1
,
97 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
98 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
99 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK
,
100 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
101 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
102 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0
,
103 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
104 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
105 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1
,
106 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
107 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
108 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2
,
109 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
110 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
111 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3
,
112 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
113 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
114 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0
,
115 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
116 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
117 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1
,
118 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
119 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
120 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0
,
121 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
122 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
123 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1
,
124 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
125 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
126 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2
,
127 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
128 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
129 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3
,
130 PAD_CTL_PKE_ENABLE
| PAD_CTL_PUE_KEEPER
|
131 PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
);
134 u32
get_board_rev(void)
136 system_rev
= get_cpu_rev();
143 #ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
144 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
145 gd
->bd
->bi_dram
[0].size
= get_ram_size((long *)PHYS_SDRAM_1
,
147 #if (CONFIG_NR_DRAM_BANKS > 1)
148 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
149 gd
->bd
->bi_dram
[1].size
= get_ram_size((long *)PHYS_SDRAM_2
,
153 gd
->ram_size
= get_ram_size((long *)PHYS_SDRAM_1
,
160 static void setup_weim(void)
162 struct weim
*pweim
= (struct weim
*)WEIM_BASE_ADDR
;
164 pweim
->csgcr1
= 0x004100b9;
165 pweim
->csgcr2
= 0x00000001;
166 pweim
->csrcr1
= 0x0a018000;
168 pweim
->cswcr1
= 0x0704a240;
171 static void setup_uart(void)
173 unsigned int pad
= PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
|
174 PAD_CTL_PUE_PULL
| PAD_CTL_DRV_HIGH
| PAD_CTL_SRE_FAST
;
175 /* console RX on Pin EIM_D25 */
176 mxc_request_iomux(MX51_PIN_EIM_D25
, IOMUX_CONFIG_ALT3
);
177 mxc_iomux_set_pad(MX51_PIN_EIM_D25
, pad
);
178 /* console TX on Pin EIM_D26 */
179 mxc_request_iomux(MX51_PIN_EIM_D26
, IOMUX_CONFIG_ALT3
);
180 mxc_iomux_set_pad(MX51_PIN_EIM_D26
, pad
);
183 #ifdef CONFIG_MXC_SPI
184 void spi_io_init(void)
186 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
187 mxc_request_iomux(MX51_PIN_CSPI1_MOSI
, IOMUX_CONFIG_ALT0
);
188 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI
,
189 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
191 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
192 mxc_request_iomux(MX51_PIN_CSPI1_MISO
, IOMUX_CONFIG_ALT0
);
193 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO
,
194 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
196 /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
197 mxc_request_iomux(MX51_PIN_CSPI1_SS0
, IOMUX_CONFIG_ALT0
);
198 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0
,
199 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
|
200 PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
203 * SS1 will be used as GPIO because of uninterrupted
204 * long SPI transmissions (GPIO4_25)
206 mxc_request_iomux(MX51_PIN_CSPI1_SS1
, IOMUX_CONFIG_ALT3
);
207 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1
,
208 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
|
209 PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
211 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
212 mxc_request_iomux(MX51_PIN_DI1_PIN11
, IOMUX_CONFIG_ALT7
);
213 mxc_iomux_set_pad(MX51_PIN_DI1_PIN11
,
214 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
|
215 PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
217 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
218 mxc_request_iomux(MX51_PIN_CSPI1_SCLK
, IOMUX_CONFIG_ALT0
);
219 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK
,
220 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
223 static void reset_peripherals(int reset
)
227 /* reset_n is on NANDF_D15 */
229 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT
);
231 #ifdef CONFIG_VISION2_HW_1_0
233 * set FEC Configuration lines
234 * set levels of FEC config lines
239 mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT
);
240 mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT
);
241 mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT
);
243 /* set direction of FEC config lines */
248 mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT
);
249 mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT
);
250 mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT
);
251 mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT
);
253 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
254 mxc_request_iomux(MX51_PIN_EIM_EB3
, IOMUX_CONFIG_ALT1
);
255 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
256 mxc_request_iomux(MX51_PIN_EIM_CS2
, IOMUX_CONFIG_ALT1
);
257 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
258 mxc_request_iomux(MX51_PIN_EIM_CS3
, IOMUX_CONFIG_ALT1
);
259 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
260 mxc_request_iomux(MX51_PIN_EIM_CS4
, IOMUX_CONFIG_ALT1
);
261 /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
262 mxc_request_iomux(MX51_PIN_NANDF_RB2
, IOMUX_CONFIG_ALT3
);
263 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
264 mxc_request_iomux(MX51_PIN_NANDF_RB3
, IOMUX_CONFIG_ALT3
);
265 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
266 mxc_request_iomux(MX51_PIN_NANDF_D9
, IOMUX_CONFIG_ALT3
);
270 * activate reset_n pin
271 * Select mux mode: ALT3 mux port: NAND D15
273 mxc_request_iomux(MX51_PIN_NANDF_D15
, IOMUX_CONFIG_ALT3
);
274 mxc_iomux_set_pad(MX51_PIN_NANDF_D15
,
275 PAD_CTL_DRV_VOT_HIGH
| PAD_CTL_DRV_MAX
);
277 /* set FEC Control lines */
278 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN
);
281 #ifdef CONFIG_VISION2_HW_1_0
283 mxc_request_iomux(MX51_PIN_EIM_CS3
, IOMUX_CONFIG_ALT3
);
284 mxc_iomux_set_pad(MX51_PIN_EIM_CS3
, 0x180);
287 mxc_request_iomux(MX51_PIN_EIM_CS2
, IOMUX_CONFIG_ALT3
);
288 mxc_iomux_set_pad(MX51_PIN_EIM_CS2
, 0x180);
291 mxc_request_iomux(MX51_PIN_EIM_EB3
, IOMUX_CONFIG_ALT3
);
292 mxc_iomux_set_pad(MX51_PIN_EIM_EB3
, 0x180);
295 mxc_request_iomux(MX51_PIN_NANDF_D9
, IOMUX_CONFIG_ALT2
);
296 mxc_iomux_set_pad(MX51_PIN_NANDF_D9
, 0x2180);
299 mxc_request_iomux(MX51_PIN_NANDF_RB3
, IOMUX_CONFIG_ALT1
);
300 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3
, 0x2180);
303 mxc_request_iomux(MX51_PIN_EIM_CS4
, IOMUX_CONFIG_ALT3
);
304 mxc_iomux_set_pad(MX51_PIN_EIM_CS4
, 0x180);
307 mxc_request_iomux(MX51_PIN_NANDF_RB2
, IOMUX_CONFIG_ALT1
);
308 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2
, 0x2180);
313 static void power_init_mx51(void)
317 /* Write needed to Power Gate 2 register */
318 val
= pmic_reg_read(REG_POWER_MISC
);
320 /* enable VCAM with 2.775V to enable read from PMIC */
321 val
= VCAMCONFIG
| VCAMEN
;
322 pmic_reg_write(REG_MODE_1
, val
);
325 * Set switchers in Auto in NORMAL mode & STANDBY mode
326 * Setup the switcher mode for SW1 & SW2
328 val
= pmic_reg_read(REG_SW_4
);
329 val
= (val
& ~((SWMODE_MASK
<< SWMODE1_SHIFT
) |
330 (SWMODE_MASK
<< SWMODE2_SHIFT
)));
331 val
|= (SWMODE_AUTO_AUTO
<< SWMODE1_SHIFT
) |
332 (SWMODE_AUTO_AUTO
<< SWMODE2_SHIFT
);
333 pmic_reg_write(REG_SW_4
, val
);
335 /* Setup the switcher mode for SW3 & SW4 */
336 val
= pmic_reg_read(REG_SW_5
);
337 val
&= ~((SWMODE_MASK
<< SWMODE4_SHIFT
) |
338 (SWMODE_MASK
<< SWMODE3_SHIFT
));
339 val
|= (SWMODE_AUTO_AUTO
<< SWMODE4_SHIFT
) |
340 (SWMODE_AUTO_AUTO
<< SWMODE3_SHIFT
);
341 pmic_reg_write(REG_SW_5
, val
);
344 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
345 val
= pmic_reg_read(REG_SETTING_0
);
346 val
&= ~(VCAM_MASK
| VGEN3_MASK
);
348 pmic_reg_write(REG_SETTING_0
, val
);
350 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
351 val
= pmic_reg_read(REG_SETTING_1
);
352 val
&= ~(VVIDEO_MASK
| VSD_MASK
| VAUDIO_MASK
);
353 val
|= VVIDEO_2_775
| VAUDIO_3_0
| VSD_1_8
;
354 pmic_reg_write(REG_SETTING_1
, val
);
356 /* Configure VGEN3 and VCAM regulators to use external PNP */
357 val
= VGEN3CONFIG
| VCAMCONFIG
;
358 pmic_reg_write(REG_MODE_1
, val
);
361 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
362 val
= VGEN3EN
| VGEN3CONFIG
| VCAMEN
| VCAMCONFIG
|
363 VVIDEOEN
| VAUDIOEN
| VSDEN
;
364 pmic_reg_write(REG_MODE_1
, val
);
366 val
= pmic_reg_read(REG_POWER_CTL2
);
368 pmic_reg_write(REG_POWER_CTL2
, val
);
375 static void setup_gpios(void)
379 /* CAM_SUP_DISn, GPIO1_7 */
380 mxc_request_iomux(MX51_PIN_GPIO1_7
, IOMUX_CONFIG_ALT0
);
381 mxc_iomux_set_pad(MX51_PIN_GPIO1_7
, 0x82);
383 /* DAB Display EN, GPIO3_1 */
384 mxc_request_iomux(MX51_PIN_DI1_PIN12
, IOMUX_CONFIG_ALT4
);
385 mxc_iomux_set_pad(MX51_PIN_DI1_PIN12
, 0x82);
387 /* WDOG_TRIGGER, GPIO3_2 */
388 mxc_request_iomux(MX51_PIN_DI1_PIN13
, IOMUX_CONFIG_ALT4
);
389 mxc_iomux_set_pad(MX51_PIN_DI1_PIN13
, 0x82);
391 /* Now we need to trigger the watchdog */
394 /* Display2 TxEN, GPIO3_3 */
395 mxc_request_iomux(MX51_PIN_DI1_D0_CS
, IOMUX_CONFIG_ALT4
);
396 mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS
, 0x82);
398 /* DAB Light EN, GPIO3_4 */
399 mxc_request_iomux(MX51_PIN_DI1_D1_CS
, IOMUX_CONFIG_ALT4
);
400 mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS
, 0x82);
402 /* AUDIO_MUTE, GPIO3_5 */
403 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN
, IOMUX_CONFIG_ALT4
);
404 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN
, 0x82);
406 /* SPARE_OUT, GPIO3_6 */
407 mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO
, IOMUX_CONFIG_ALT4
);
408 mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO
, 0x82);
410 /* BEEPER_EN, GPIO3_26 */
411 mxc_request_iomux(MX51_PIN_NANDF_D14
, IOMUX_CONFIG_ALT3
);
412 mxc_iomux_set_pad(MX51_PIN_NANDF_D14
, 0x82);
414 /* POWER_OFF, GPIO3_27 */
415 mxc_request_iomux(MX51_PIN_NANDF_D13
, IOMUX_CONFIG_ALT3
);
416 mxc_iomux_set_pad(MX51_PIN_NANDF_D13
, 0x82);
418 /* FRAM_WE, GPIO3_30 */
419 mxc_request_iomux(MX51_PIN_NANDF_D10
, IOMUX_CONFIG_ALT3
);
420 mxc_iomux_set_pad(MX51_PIN_NANDF_D10
, 0x82);
422 /* EXPANSION_EN, GPIO4_26 */
423 mxc_request_iomux(MX51_PIN_CSPI1_RDY
, IOMUX_CONFIG_ALT3
);
424 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY
, 0x82);
427 * Set GPIO1_4 to high and output; it is used to reset
428 * the system on reboot
431 mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT
);
434 mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT
);
435 for (i
= 65; i
< 71; i
++) {
437 mxc_gpio_direction(i
, MXC_GPIO_DIRECTION_OUT
);
441 mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT
);
443 /* Set POWER_OFF high */
445 mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT
);
448 mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT
);
450 mxc_gpio_set(122, 0);
451 mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT
);
453 mxc_gpio_set(121, 1);
454 mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT
);
459 static void setup_fec(void)
462 mxc_request_iomux(MX51_PIN_EIM_EB2
, IOMUX_CONFIG_ALT3
);
463 mxc_iomux_set_pad(MX51_PIN_EIM_EB2
, 0x1FD);
466 mxc_request_iomux(MX51_PIN_NANDF_CS3
, IOMUX_CONFIG_ALT2
);
467 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3
, 0x2004);
470 mxc_request_iomux(MX51_PIN_EIM_CS3
, IOMUX_CONFIG_ALT3
);
471 mxc_iomux_set_pad(MX51_PIN_EIM_CS3
, 0x180);
474 mxc_request_iomux(MX51_PIN_EIM_CS2
, IOMUX_CONFIG_ALT3
);
475 mxc_iomux_set_pad(MX51_PIN_EIM_CS2
, 0x180);
478 mxc_request_iomux(MX51_PIN_EIM_EB3
, IOMUX_CONFIG_ALT3
);
479 mxc_iomux_set_pad(MX51_PIN_EIM_EB3
, 0x180);
482 mxc_request_iomux(MX51_PIN_NANDF_D9
, IOMUX_CONFIG_ALT2
);
483 mxc_iomux_set_pad(MX51_PIN_NANDF_D9
, 0x2180);
486 mxc_request_iomux(MX51_PIN_NANDF_CS6
, IOMUX_CONFIG_ALT2
);
487 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6
, 0x2004);
490 mxc_request_iomux(MX51_PIN_NANDF_CS5
, IOMUX_CONFIG_ALT2
);
491 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5
, 0x2004);
494 mxc_request_iomux(MX51_PIN_NANDF_CS4
, IOMUX_CONFIG_ALT2
);
495 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4
, 0x2004);
498 mxc_request_iomux(MX51_PIN_NANDF_D8
, IOMUX_CONFIG_ALT2
);
499 mxc_iomux_set_pad(MX51_PIN_NANDF_D8
, 0x2004);
502 mxc_request_iomux(MX51_PIN_NANDF_CS7
, IOMUX_CONFIG_ALT1
);
503 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7
, 0x2004);
506 mxc_request_iomux(MX51_PIN_NANDF_CS2
, IOMUX_CONFIG_ALT2
);
507 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2
, 0x2004);
510 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT
, IOMUX_CONFIG_ALT1
);
511 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT
, 0x2180);
514 mxc_request_iomux(MX51_PIN_NANDF_RB2
, IOMUX_CONFIG_ALT1
);
515 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2
, 0x2180);
518 mxc_request_iomux(MX51_PIN_NANDF_RB3
, IOMUX_CONFIG_ALT1
);
519 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3
, 0x2180);
522 mxc_request_iomux(MX51_PIN_EIM_CS5
, IOMUX_CONFIG_ALT3
);
523 mxc_iomux_set_pad(MX51_PIN_EIM_CS5
, 0x180);
526 mxc_request_iomux(MX51_PIN_EIM_CS4
, IOMUX_CONFIG_ALT3
);
527 mxc_iomux_set_pad(MX51_PIN_EIM_CS4
, 0x180);
530 mxc_request_iomux(MX51_PIN_NANDF_D11
, IOMUX_CONFIG_ALT2
);
531 mxc_iomux_set_pad(MX51_PIN_NANDF_D11
, 0x2180);
534 struct fsl_esdhc_cfg esdhc_cfg
[1] = {
535 {MMC_SDHC1_BASE_ADDR
, 1},
538 int get_mmc_getcd(u8
*cd
, struct mmc
*mmc
)
540 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
542 if (cfg
->esdhc_base
== MMC_SDHC1_BASE_ADDR
)
543 *cd
= mxc_gpio_get(0);
550 #ifdef CONFIG_FSL_ESDHC
551 int board_mmc_init(bd_t
*bis
)
553 mxc_request_iomux(MX51_PIN_SD1_CMD
,
554 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
555 mxc_request_iomux(MX51_PIN_SD1_CLK
,
556 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
557 mxc_request_iomux(MX51_PIN_SD1_DATA0
,
558 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
559 mxc_request_iomux(MX51_PIN_SD1_DATA1
,
560 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
561 mxc_request_iomux(MX51_PIN_SD1_DATA2
,
562 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
563 mxc_request_iomux(MX51_PIN_SD1_DATA3
,
564 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
565 mxc_iomux_set_pad(MX51_PIN_SD1_CMD
,
566 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
567 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
569 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
570 mxc_iomux_set_pad(MX51_PIN_SD1_CLK
,
571 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
572 PAD_CTL_HYS_NONE
| PAD_CTL_47K_PU
|
574 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
575 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0
,
576 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
577 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
579 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
580 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1
,
581 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
582 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
584 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
585 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2
,
586 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
587 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
589 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
590 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3
,
591 PAD_CTL_DRV_MAX
| PAD_CTL_DRV_VOT_HIGH
|
592 PAD_CTL_HYS_ENABLE
| PAD_CTL_100K_PD
|
594 PAD_CTL_PKE_ENABLE
| PAD_CTL_SRE_FAST
);
595 mxc_request_iomux(MX51_PIN_GPIO1_0
,
596 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
597 mxc_iomux_set_pad(MX51_PIN_GPIO1_0
,
599 mxc_request_iomux(MX51_PIN_GPIO1_1
,
600 IOMUX_CONFIG_ALT0
| IOMUX_CONFIG_SION
);
601 mxc_iomux_set_pad(MX51_PIN_GPIO1_1
,
604 return fsl_esdhc_initialize(bis
, &esdhc_cfg
[0]);
608 int board_early_init_f(void)
612 init_drive_strength();
614 /* Setup debug led */
616 mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT
);
617 mxc_request_iomux(MX51_PIN_GPIO1_6
, IOMUX_CONFIG_ALT0
);
618 mxc_iomux_set_pad(MX51_PIN_GPIO1_6
, PAD_CTL_DRV_MAX
| PAD_CTL_SRE_FAST
);
620 /* wait a little while to give the pll time to settle */
635 #ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
636 board_early_init_f();
638 gd
->bd
->bi_arch_number
= MACH_TYPE_TTC_VISION2
; /* board id for linux */
639 /* address of boot parameters */
640 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
645 int board_late_init(void)
649 reset_peripherals(1);
651 reset_peripherals(0);
654 /* Early revisions require a second reset */
655 #ifdef CONFIG_VISION2_HW_1_0
656 reset_peripherals(1);
658 reset_peripherals(0);
667 u32 system_rev
= get_cpu_rev();
669 struct src
*src_regs
= (struct src
*)SRC_BASE_ADDR
;
671 puts("Board: TTControl Vision II CPU V");
673 switch (system_rev
& 0xff) {
692 cause
= src_regs
->srsr
;
705 printf("unknown 0x%x", cause
);