board/wepep250/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2001, 2002 ETC s.r.o.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  17  * 02111-1307, USA.
  18  *
  19  * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
  20  * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
  21  *
  22  * This file is taken from OpenWinCE project hosted by SourceForge.net
  23  *
  24  * Documentation:
  25  * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
  26  *     Developer's Manual", February 2002, Order Number: 278522-001
  27  * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
  28  *     Revision 1.0, February 2002
  29  * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
  30  *     Revision 1.0, February 2002
  31  *
  32 */
  33
  34 #include <config.h>
  35 #include <version.h>
  36 #include <asm/arch/pxa-regs.h>
  37
  38 .globl lowlevel_init
  39 lowlevel_init:
  40
  41         mov     r10, lr
  42
  43 /*      setup memory - see 6.12 in [1]
  44  *      Step 1  - wait 200 us
  45  */
  46         mov     r0,#0x2700                      /* wait 200 us @ 99.5 MHz */
  47 1:      subs    r0, r0, #1
  48         bne     1b
  49 /*      TODO: complete step 1 for Synchronous Static memory*/
  50
  51         ldr     r0, =0x48000000                 /* MC_BASE */
  52
  53
  54 /*      step 1.a - setup MSCx
  55  */
  56         ldr     r1, =0x000012B3                 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
  57         str     r1, [r0, #0x8]                  /* MSC0_OFFSET */
  58
  59 /*      step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
  60  *      see AUTO REFRESH chapter in section D. in [2] and in [3]
  61  *      DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
  62  *      DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
  63  *      TODO: complete for Synchronous Static memory
  64  */
  65         ldr     r1, [r0, #4]                    /* MDREFR_OFFSET */
  66         ldr     r2, =0x01000FFF                 /* MDREFR_K1FREE | MDREFR_DRI_MASK */
  67         bic     r1, r1, r2
  68 #if defined( WEP_SDRAM_K4S281633 )
  69         orr     r1, r1, #48                     /* MDREFR_DRI(48) */
  70 #elif defined( WEP_SDRAM_K4S561633 )
  71         orr     r1, r1, #24                     /* MDREFR_DRI(24) */
  72 #else
  73 #error SDRAM chip is not defined
  74 #endif
  75
  76         str     r1, [r0, #4]                    /* MDREFR_OFFSET */
  77
  78 /*      Step 2 - only for Synchronous Static memory (TODO)
  79  *
  80  *      Step 3 - same as step 4
  81  *
  82  *      Step 4
  83  *
  84  *      Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
  85  */
  86         orr     r1, r1, #0x00010000             /* MDREFR_K1RUN */
  87         bic     r1, r1, #0x00020000             /* MDREFR_K1DB2 */
  88         str     r1, [r0, #4]                    /* MDREFR_OFFSET */
  89
  90 /*      Step 4.b - clear MDREFR:SLFRSH */
  91         bic     r1, r1, #0x00400000             /* MDREFR_SLFRSH */
  92         str     r1, [r0, #4]                    /* MDREFR_OFFSET */
  93
  94 /*      Step 4.c - set MDREFR:E1PIN */
  95         orr     r1, r1, #0x00008000             /* MDREFR_E1PIN */
  96         str     r1, [r0, #4]                    /* MDREFR_OFFSET */
  97
  98 /*      Step 4.d - automatically done
  99  *
 100  *      Steps 4.e and 4.f - configure SDRAM
 101  */
 102 #if defined( WEP_SDRAM_K4S281633 )
 103         ldr     r1, =0x00000AA8                 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
 104 #elif defined( WEP_SDRAM_K4S561633 )
 105         ldr     r1, =0x00000AC8                 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
 106 #else
 107 #error SDRAM chip is not defined
 108 #endif
 109         str     r1, [r0, #0]                    /* MDCNFG_OFFSET */
 110
 111 /*      Step 5 - wait at least 200 us for SDRAM
 112  *      see section B. in [2]
 113  */
 114         mov     r2,#0x2700                      /* wait 200 us @ 99.5 MHz */
 115 1:      subs    r2, r2, #1
 116         bne     1b
 117
 118 /*      Step 6 - after reset dcache is disabled, so automatically done
 119  *
 120  *      Step 7 - eight refresh cycles
 121  */
 122         mov     r2, #0xA0000000
 123         ldr     r3, [r2]
 124         ldr     r3, [r2]
 125         ldr     r3, [r2]
 126         ldr     r3, [r2]
 127         ldr     r3, [r2]
 128         ldr     r3, [r2]
 129         ldr     r3, [r2]
 130         ldr     r3, [r2]
 131
 132 /*      Step 8 - we don't need dcache now
 133  *
 134  *      Step 9 - enable SDRAM partition 0
 135  */
 136         orr     r1, r1, #1                      /* MDCNFG_DE0 */
 137         str     r1, [r0, #0]                    /* MDCNFG_OFFSET */
 138
 139 /*      Step 10 - write MDMRS */
 140         mov     r1, #0
 141         str     r1, [r0, #0x40]                 /* MDMRS_OFFSET */
 142
 143 /*      Step 11 - optional (TODO) */
 144
 145         mov     pc,r10