board/xes/xpedite550x/ddr.c

   1 /*
   2  * Copyright 2010 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <i2c.h>
  26
  27 #include <asm/fsl_ddr_sdram.h>
  28 #include <asm/fsl_ddr_dimm_params.h>
  29
  30 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
  31 {
  32         i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
  33                  sizeof(ddr3_spd_eeprom_t));
  34 }
  35
  36 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
  37                       unsigned int ctrl_num)
  38 {
  39         unsigned int i;
  40         unsigned int i2c_address = 0;
  41
  42         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  43                 if (ctrl_num == 0 && i == 0)
  44                         i2c_address = SPD_EEPROM_ADDRESS1;
  45                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  46         }
  47 }
  48
  49 unsigned int fsl_ddr_get_mem_data_rate(void)
  50 {
  51         return get_ddr_freq(0);
  52 }
  53
  54 /*
  55  *     There are traditionally three board-specific SDRAM timing parameters
  56  *     which must be calculated based on the particular PCB artwork.  These are:
  57  *     1.) CPO (Read Capture Delay)
  58  *             - TIMING_CFG_2 register
  59  *             Source: Calculation based on board trace lengths and
  60  *                     chip-specific internal delays.
  61  *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
  62  *             - DDR_SDRAM_CLK_CNTL register
  63  *             Source: Signal Integrity Simulations
  64  *     3.) 2T Timing on Addr/Ctl
  65  *             - TIMING_CFG_2 register
  66  *             Source: Signal Integrity Simulations
  67  *             Usually only needed with heavy load/very high speed (>DDR2-800)
  68  *
  69  *     ====== XPedite550x DDR3-800 read delay calculations ======
  70  *
  71  *     The P2020 processor provides an autoleveling option. Setting CPO to
  72  *     0x1f enables this auto configuration.
  73  */
  74
  75 typedef struct {
  76         unsigned short datarate_mhz_low;
  77         unsigned short datarate_mhz_high;
  78         unsigned char clk_adjust;
  79         unsigned char cpo;
  80 } board_specific_parameters_t;
  81
  82 const board_specific_parameters_t board_specific_parameters[][20] = {
  83         {
  84                 /* Controller 0 */
  85                 {
  86                         /* DDR3-600/667 */
  87                         .datarate_mhz_low       = 500,
  88                         .datarate_mhz_high      = 750,
  89                         .clk_adjust             = 5,
  90                         .cpo                    = 31,
  91                 },
  92                 {
  93                         /* DDR3-800 */
  94                         .datarate_mhz_low       = 750,
  95                         .datarate_mhz_high      = 850,
  96                         .clk_adjust             = 5,
  97                         .cpo                    = 31,
  98                 },
  99         },
 100 };
 101
 102 void fsl_ddr_board_options(memctl_options_t *popts,
 103                                 dimm_params_t *pdimm,
 104                                 unsigned int ctrl_num)
 105 {
 106         const board_specific_parameters_t *pbsp =
 107                                 &(board_specific_parameters[ctrl_num][0]);
 108         u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
 109                                 sizeof(board_specific_parameters[0][0]);
 110         u32 i;
 111         ulong ddr_freq;
 112
 113         /*
 114          * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
 115          * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
 116          * there are two dimms in the controller, set odt_rd_cfg to 3 and
 117          * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
 118          */
 119         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 120                 if (i&1) {      /* odd CS */
 121                         popts->cs_local_opts[i].odt_rd_cfg = 0;
 122                         popts->cs_local_opts[i].odt_wr_cfg = 0;
 123                 } else {        /* even CS */
 124                         if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 125                                 popts->cs_local_opts[i].odt_rd_cfg = 0;
 126                                 popts->cs_local_opts[i].odt_wr_cfg = 4;
 127                         } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 128                                 popts->cs_local_opts[i].odt_rd_cfg = 3;
 129                                 popts->cs_local_opts[i].odt_wr_cfg = 3;
 130                         }
 131                 }
 132         }
 133
 134         /*
 135          * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 136          * freqency and n_banks specified in board_specific_parameters table.
 137          */
 138         ddr_freq = get_ddr_freq(0) / 1000000;
 139
 140         for (i = 0; i < num_params; i++) {
 141                 if (ddr_freq >= pbsp->datarate_mhz_low &&
 142                     ddr_freq <= pbsp->datarate_mhz_high) {
 143                         popts->clk_adjust = pbsp->clk_adjust;
 144                         popts->cpo_override = pbsp->cpo;
 145                         popts->twoT_en = 0;
 146                 }
 147                 pbsp++;
 148         }
 149
 150         /*
 151          * Factors to consider for half-strength driver enable:
 152          *      - number of DIMMs installed
 153          */
 154         popts->half_strength_driver_enable = 0;
 155
 156         /*
 157          * Enable on-die termination.
 158          * From the Micron Technical Node TN-41-04, RTT_Nom should typically
 159          * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
 160          * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
 161          */
 162         popts->rtt_override = 1;
 163         popts->rtt_override_value = 3;
 164 }