board/xm250/lowlevel_init.S

   1 /*
   2  * Most of this taken from Redboot hal_platform_setup.h with cleanup
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <config.h>
  24 #include <version.h>
  25 #include <asm/arch/pxa-regs.h>
  26
  27 DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
  28
  29 /* wait for coprocessor write complete */
  30         .macro CPWAIT reg
  31         mrc     p15,0,\reg,c2,c0,0
  32         mov     \reg,\reg
  33         sub     pc,pc,#4
  34         .endm
  35 /*
  36         .macro SET_LED val
  37         ldr     r6, =CRADLE_LED_CLR_REG
  38         ldr     r7, =0
  39         str     r7, [r6]
  40         ldr     r6, =CRADLE_LED_SET_REG
  41         ldr     r7, =\val
  42         str     r7, [r6]
  43         .endm
  44 */
  45
  46 .globl lowlevel_init
  47 lowlevel_init:
  48
  49         mov     r10, lr
  50
  51         /* Set up GPIO pins first */
  52
  53         ldr     r0,   =GPSR0
  54         ldr     r1,   =CONFIG_SYS_GPSR0_VAL
  55         str     r1,   [r0]
  56
  57         ldr     r0,   =GPSR1
  58         ldr     r1,   =CONFIG_SYS_GPSR1_VAL
  59         str     r1,   [r0]
  60
  61         ldr     r0,   =GPSR2
  62         ldr     r1,   =CONFIG_SYS_GPSR2_VAL
  63         str     r1,   [r0]
  64
  65         ldr     r0,   =GPCR0
  66         ldr     r1,   =CONFIG_SYS_GPCR0_VAL
  67         str     r1,   [r0]
  68
  69         ldr     r0,   =GPCR1
  70         ldr     r1,   =CONFIG_SYS_GPCR1_VAL
  71         str     r1,   [r0]
  72
  73         ldr     r0,   =GPCR2
  74         ldr     r1,   =CONFIG_SYS_GPCR2_VAL
  75         str     r1,   [r0]
  76
  77         ldr     r0,   =GRER0
  78         ldr     r1,   =CONFIG_SYS_GRER0_VAL
  79         str     r1,   [r0]
  80
  81         ldr     r0,   =GRER1
  82         ldr     r1,   =CONFIG_SYS_GRER1_VAL
  83         str     r1,   [r0]
  84
  85         ldr     r0,   =GRER2
  86         ldr     r1,   =CONFIG_SYS_GRER2_VAL
  87         str     r1,   [r0]
  88
  89         ldr     r0,   =GFER0
  90         ldr     r1,   =CONFIG_SYS_GFER0_VAL
  91         str     r1,   [r0]
  92
  93         ldr     r0,   =GFER1
  94         ldr     r1,   =CONFIG_SYS_GFER1_VAL
  95         str     r1,   [r0]
  96
  97         ldr     r0,   =GFER2
  98         ldr     r1,   =CONFIG_SYS_GFER2_VAL
  99         str     r1,   [r0]
 100
 101         ldr     r0,   =GPDR0
 102         ldr     r1,   =CONFIG_SYS_GPDR0_VAL
 103         str     r1,   [r0]
 104
 105         ldr     r0,   =GPDR1
 106         ldr     r1,   =CONFIG_SYS_GPDR1_VAL
 107         str     r1,   [r0]
 108
 109         ldr     r0,   =GPDR2
 110         ldr     r1,   =CONFIG_SYS_GPDR2_VAL
 111         str     r1,   [r0]
 112
 113         ldr     r0,   =GAFR0_L
 114         ldr     r1,   =CONFIG_SYS_GAFR0_L_VAL
 115         str     r1,   [r0]
 116
 117         ldr     r0,   =GAFR0_U
 118         ldr     r1,   =CONFIG_SYS_GAFR0_U_VAL
 119         str     r1,   [r0]
 120
 121         ldr     r0,   =GAFR1_L
 122         ldr     r1,   =CONFIG_SYS_GAFR1_L_VAL
 123         str     r1,   [r0]
 124
 125         ldr     r0,   =GAFR1_U
 126         ldr     r1,   =CONFIG_SYS_GAFR1_U_VAL
 127         str     r1,   [r0]
 128
 129         ldr     r0,   =GAFR2_L
 130         ldr     r1,   =CONFIG_SYS_GAFR2_L_VAL
 131         str     r1,   [r0]
 132
 133         ldr     r0,   =GAFR2_U
 134         ldr     r1,   =CONFIG_SYS_GAFR2_U_VAL
 135         str     r1,   [r0]
 136
 137         /* enable GPIO pins */
 138         ldr     r0,   =PSSR
 139         ldr     r1,   =CONFIG_SYS_PSSR_VAL
 140         str     r1,   [r0]
 141
 142         /* SET_LED 1 */
 143
 144         ldr     r3, =MSC1               /* low - bank 2 Lubbock Registers / SRAM */
 145         ldr     r2, =CONFIG_SYS_MSC1_VAL        /* high - bank 3 Ethernet Controller */
 146         str     r2, [r3]                /* need to set MSC1 before trying to write to the HEX LEDs */
 147         ldr     r2, [r3]                /* need to read it back to make sure the value latches (see MSC section of manual) */
 148
 149
 150 /*********************************************************************
 151  *  Initlialize Memory Controller
 152  *
 153  *  See PXA250 Operating System Developer's Guide
 154  *
 155  *  pause for 200 uSecs- allow internal clocks to settle
 156  *  *Note: only need this if hard reset... doing it anyway for now
 157  */
 158
 159         @ Step 1
 160         @ ---- Wait 200 usec
 161         ldr     r3, =OSCR       @ reset the OS Timer Count to zero
 162         mov     r2, #0
 163         str     r2, [r3]
 164         ldr     r4, =0x300      @ really 0x2E1 is about 200usec, so 0x300 should be plenty
 165 1:
 166         ldr     r2, [r3]
 167         cmp     r4, r2
 168         bgt     1b
 169
 170         /* SET_LED 2 */
 171
 172 mem_init:
 173         @ get memory controller base address
 174         ldr     r1,  =MEMC_BASE
 175
 176
 177 @****************************************************************************
 178 @  Step 2
 179 @
 180
 181         @ Step 2a
 182         @ write msc0, read back to ensure data latches
 183         @
 184         ldr     r2,   =CONFIG_SYS_MSC0_VAL
 185         str     r2,   [r1, #MSC0_OFFSET]
 186         ldr     r2,   [r1, #MSC0_OFFSET]
 187
 188         @ write msc1
 189         ldr     r2,  =CONFIG_SYS_MSC1_VAL
 190         str     r2,  [r1, #MSC1_OFFSET]
 191         ldr     r2,  [r1, #MSC1_OFFSET]
 192
 193         @ write msc2
 194         ldr     r2,  =CONFIG_SYS_MSC2_VAL
 195         str     r2,  [r1, #MSC2_OFFSET]
 196         ldr     r2,  [r1, #MSC2_OFFSET]
 197
 198         @ Step 2b
 199         @ write mecr
 200         ldr     r2,  =CONFIG_SYS_MECR_VAL
 201         str     r2,  [r1, #MECR_OFFSET]
 202
 203         @ write mcmem0
 204         ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 205         str     r2,  [r1, #MCMEM0_OFFSET]
 206
 207         @ write mcmem1
 208         ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 209         str     r2,  [r1, #MCMEM1_OFFSET]
 210
 211         @ write mcatt0
 212         ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 213         str     r2,  [r1, #MCATT0_OFFSET]
 214
 215         @ write mcatt1
 216         ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 217         str     r2,  [r1, #MCATT1_OFFSET]
 218
 219         @ write mcio0
 220         ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 221         str     r2,  [r1, #MCIO0_OFFSET]
 222
 223         @ write mcio1
 224         ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 225         str     r2,  [r1, #MCIO1_OFFSET]
 226
 227         /*SET_LED 3 */
 228
 229         @ Step 2c
 230         @ fly-by-dma is defeatured on this part
 231         @ write flycnfg
 232         @ldr    r2,  =CONFIG_SYS_FLYCNFG_VAL
 233         @str    r2,  [r1, #FLYCNFG_OFFSET]
 234
 235 /* FIXME Does this sequence really make sense */
 236 #ifdef REDBOOT_WAY
 237         @ Step 2d
 238         @ get the mdrefr settings
 239         ldr     r3,  =CONFIG_SYS_MDREFR_VAL
 240
 241         @ extract DRI field (we need a valid DRI field)
 242         @
 243         ldr     r2,  =0xFFF
 244
 245         @ valid DRI field in r3
 246         @
 247         and     r3,  r3,  r2
 248
 249         @ get the reset state of MDREFR
 250         @
 251         ldr     r4,  [r1, #MDREFR_OFFSET]
 252
 253         @ clear the DRI field
 254         @
 255         bic     r4,  r4,  r2
 256
 257         @ insert the valid DRI field loaded above
 258         @
 259         orr     r4,  r4,  r3
 260
 261         @ write back mdrefr
 262         @
 263         str     r4,  [r1, #MDREFR_OFFSET]
 264
 265         @ *Note: preserve the mdrefr value in r4 *
 266
 267         /*SET_LED 4 */
 268
 269 @****************************************************************************
 270 @  Step 3
 271 @
 272 @ NO SRAM
 273
 274         mov   pc, r10
 275
 276
 277 @****************************************************************************
 278 @  Step 4
 279 @
 280
 281         @ Assumes previous mdrefr value in r4, if not then read current mdrefr
 282
 283         @ clear the free-running clock bits
 284         @ (clear K0Free, K1Free, K2Free
 285         @
 286         bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
 287
 288         @ set K0RUN for CPLD clock
 289         @
 290         orr     r4,  r4, #0x00002000
 291
 292         @ set K1RUN if bank 0 installed
 293         @
 294         orr     r4,  r4, #0x00010000
 295
 296         @ write back mdrefr
 297         @
 298         str     r4,  [r1, #MDREFR_OFFSET]
 299         ldr     r4,  [r1, #MDREFR_OFFSET]
 300
 301         @ deassert SLFRSH
 302         @
 303         bic     r4,  r4,  #0x00400000
 304
 305         @ write back mdrefr
 306         @
 307         str     r4,  [r1, #MDREFR_OFFSET]
 308
 309         @ assert E1PIN
 310         @
 311         orr     r4,  r4,  #0x00008000
 312
 313         @ write back mdrefr
 314         @
 315         str     r4,  [r1, #MDREFR_OFFSET]
 316         ldr     r4,  [r1, #MDREFR_OFFSET]
 317         nop
 318         nop
 319 #else
 320         @ Step 2d
 321         @ get the mdrefr settings
 322         ldr     r4,  =CONFIG_SYS_MDREFR_VAL
 323
 324         @ write back mdrefr
 325         @
 326         str     r4,  [r1, #MDREFR_OFFSET]
 327
 328         @  Step 4
 329
 330         @ set K0RUN for FLASH clock
 331         @
 332         orr     r4,  r4, #0x00002000
 333
 334         @ set K1RUN for bank DRAM 0
 335         @
 336         orr     r4,  r4, #0x00010000
 337
 338         @ set K2RUN for bank PLD
 339         @
 340         orr     r4,  r4, #0x00040000
 341
 342         @ write back mdrefr
 343         @
 344         str     r4,  [r1, #MDREFR_OFFSET]
 345         ldr     r4,  [r1, #MDREFR_OFFSET]
 346
 347         @ deassert SLFRSH
 348         @
 349         bic     r4,  r4,  #0x00400000
 350
 351         @ write back mdrefr
 352         @
 353         str     r4,  [r1, #MDREFR_OFFSET]
 354
 355         @ assert E1PIN
 356         @
 357         orr     r4,  r4,  #0x00008000
 358
 359         @ write back mdrefr
 360         @
 361         str     r4,  [r1, #MDREFR_OFFSET]
 362         ldr     r4,  [r1, #MDREFR_OFFSET]
 363         nop
 364         nop
 365 #endif
 366
 367         @ Step 4d
 368         @ fetch platform value of mdcnfg
 369         @
 370         ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 371
 372         @ disable all sdram banks
 373         @
 374         bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
 375         bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
 376
 377         @ program banks 0/1 for bus width
 378         @
 379         bic     r2,  r2,  #MDCNFG_DWID0         @0=32-bit
 380
 381         @ write initial value of mdcnfg, w/o enabling sdram banks
 382         @
 383         str     r2,  [r1, #MDCNFG_OFFSET]
 384
 385         @ Step 4e
 386         @ pause for 200 uSecs
 387         @
 388         ldr     r3, =OSCR       @ reset the OS Timer Count to zero
 389         mov     r2, #0
 390         str     r2, [r3]
 391         ldr     r4, =0x300      @ really 0x2E1 is about 200usec, so 0x300 should be plenty
 392 1:
 393         ldr     r2, [r3]
 394         cmp     r4, r2
 395         bgt     1b
 396
 397         /*SET_LED 5 */
 398
 399         /* Why is this here??? */
 400         mov     r0, #0x78               @turn everything off
 401         mcr     p15, 0, r0, c1, c0, 0   @(caches off, MMU off, etc.)
 402
 403         @ Step 4f
 404         @ Access memory *not yet enabled* for CBR refresh cycles (8)
 405         @ - CBR is generated for all banks
 406
 407         ldr     r2, =CONFIG_SYS_DRAM_BASE
 408         str     r2, [r2]
 409         str     r2, [r2]
 410         str     r2, [r2]
 411         str     r2, [r2]
 412         str     r2, [r2]
 413         str     r2, [r2]
 414         str     r2, [r2]
 415         str     r2, [r2]
 416
 417         @ Step 4g
 418         @get memory controller base address
 419         @
 420         ldr     r1,  =MEMC_BASE
 421
 422         @fetch current mdcnfg value
 423         @
 424         ldr     r3,  [r1, #MDCNFG_OFFSET]
 425
 426         @enable sdram bank 0 if installed (must do for any populated bank)
 427         @
 428         orr     r3,  r3,  #MDCNFG_DE0
 429
 430         @write back mdcnfg, enabling the sdram bank(s)
 431         @
 432         str     r3,  [r1, #MDCNFG_OFFSET]
 433
 434         @ Step 4h
 435         @ write mdmrs
 436         @
 437         ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 438         str     r2,  [r1, #MDMRS_OFFSET]
 439
 440         @ Done Memory Init
 441
 442         /*SET_LED 6 */
 443
 444         @********************************************************************
 445         @ Disable (mask) all interrupts at the interrupt controller
 446         @
 447
 448         @ clear the interrupt level register (use IRQ, not FIQ)
 449         @
 450         mov     r1, #0
 451         ldr     r2,  =ICLR
 452         str     r1,  [r2]
 453
 454         @ Set interrupt mask register
 455         @
 456         ldr     r1,  =CONFIG_SYS_ICMR_VAL
 457         ldr     r2,  =ICMR
 458         str     r1,  [r2]
 459
 460         @ ********************************************************************
 461         @ Disable the peripheral clocks, and set the core clock
 462         @
 463
 464         @ Turn Off ALL on-chip peripheral clocks for re-configuration
 465         @
 466         ldr     r1,  =CKEN
 467         mov     r2,  #0
 468         str     r2,  [r1]
 469
 470         @ set core clocks
 471         @
 472         ldr     r2,  =CONFIG_SYS_CCCR_VAL
 473         ldr     r1,  =CCCR
 474         str     r2,  [r1]
 475
 476 #ifdef ENABLE32KHZ
 477         @ enable the 32Khz oscillator for RTC and PowerManager
 478         @
 479         ldr     r1,  =OSCC
 480         mov     r2,  #OSCC_OON
 481         str     r2,  [r1]
 482
 483         @ NOTE:  spin here until OSCC.OOK get set,
 484         @        meaning the PLL has settled.
 485         @
 486 60:
 487         ldr     r2, [r1]
 488         ands    r2, r2, #1
 489         beq     60b
 490 #endif
 491
 492         @ Turn on needed clocks
 493         @
 494         ldr     r1,  =CKEN
 495         ldr     r2,  =CONFIG_SYS_CKEN_VAL
 496         str     r2,  [r1]
 497
 498         /*SET_LED 7 */
 499
 500 /* Is this needed???? */
 501 #define NODEBUG
 502 #ifdef NODEBUG
 503         /*Disable software and data breakpoints */
 504         mov     r0,#0
 505         mcr     p15,0,r0,c14,c8,0       /* ibcr0 */
 506         mcr     p15,0,r0,c14,c9,0       /* ibcr1 */
 507         mcr     p15,0,r0,c14,c4,0       /* dbcon */
 508
 509         /*Enable all debug functionality */
 510         mov     r0,#0x80000000
 511         mcr     p14,0,r0,c10,c0,0       /* dcsr */
 512
 513 #endif
 514
 515         /*SET_LED 8 */
 516
 517         mov     pc, r10
 518
 519 @ End lowlevel_init