2 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 #define BOOT_SMALL_FLASH 32 /* 00100000 */
32 #define FLASH_ONBD_N 2 /* 00000010 */
33 #define FLASH_SRAM_SEL 1 /* 00000001 */
35 long int fixed_sdram (void);
37 int board_early_init_f(void)
40 /* TBS: Setup the GPIO access for the user LEDs */
41 mfsdr(sdr_pfc0
, sdrreg
);
42 mtsdr(sdr_pfc0
, (sdrreg
& ~0x00000100) | 0x00000E00);
43 out32(CONFIG_SYS_GPIO_BASE
+ 0x018, (USR_LED0
| USR_LED1
| USR_LED2
| USR_LED3
));
49 /*--------------------------------------------------------------------
50 * Setup the external bus controller/chip selects
51 *-------------------------------------------------------------------*/
53 /* set the bus controller */
54 mtebc (pb0ap
, 0x04055200); /* FLASH/SRAM */
55 mtebc (pb0cr
, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
56 mtebc (pb1ap
, 0x04055200); /* FLASH/SRAM */
57 mtebc (pb1cr
, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */
59 /*--------------------------------------------------------------------
60 * Setup the interrupt controller polarities, triggers, etc.
61 *-------------------------------------------------------------------*/
63 * Because of the interrupt handling rework to handle 440GX interrupts
64 * with the common code, we needed to change names of the UIC registers.
65 * Here the new relationship:
67 * U-Boot name 440GX name
68 * -----------------------
74 mtdcr (uic1sr
, 0xffffffff); /* clear all */
75 mtdcr (uic1er
, 0x00000000); /* disable all */
76 mtdcr (uic1cr
, 0x00000003); /* SMI & UIC1 crit are critical */
77 mtdcr (uic1pr
, 0xfffffe00); /* per ref-board manual */
78 mtdcr (uic1tr
, 0x01c00000); /* per ref-board manual */
79 mtdcr (uic1vr
, 0x00000001); /* int31 highest, base=0x000 */
80 mtdcr (uic1sr
, 0xffffffff); /* clear all */
82 mtdcr (uic2sr
, 0xffffffff); /* clear all */
83 mtdcr (uic2er
, 0x00000000); /* disable all */
84 mtdcr (uic2cr
, 0x00000000); /* all non-critical */
85 mtdcr (uic2pr
, 0xffffc0ff); /* per ref-board manual */
86 mtdcr (uic2tr
, 0x00ff8000); /* per ref-board manual */
87 mtdcr (uic2vr
, 0x00000001); /* int31 highest, base=0x000 */
88 mtdcr (uic2sr
, 0xffffffff); /* clear all */
90 mtdcr (uic3sr
, 0xffffffff); /* clear all */
91 mtdcr (uic3er
, 0x00000000); /* disable all */
92 mtdcr (uic3cr
, 0x00000000); /* all non-critical */
93 mtdcr (uic3pr
, 0xffffffff); /* per ref-board manual */
94 mtdcr (uic3tr
, 0x00ff8c0f); /* per ref-board manual */
95 mtdcr (uic3vr
, 0x00000001); /* int31 highest, base=0x000 */
96 mtdcr (uic3sr
, 0xffffffff); /* clear all */
98 mtdcr (uic0sr
, 0xfc000000); /* clear all */
99 mtdcr (uic0er
, 0x00000000); /* disable all */
100 mtdcr (uic0cr
, 0x00000000); /* all non-critical */
101 mtdcr (uic0pr
, 0xfc000000); /* */
102 mtdcr (uic0tr
, 0x00000000); /* */
103 mtdcr (uic0vr
, 0x00000001); /* */
111 int checkboard (void)
113 printf ("Board: XES XPedite1000 440GX\n");
119 phys_size_t
initdram (int board_type
)
123 #if defined(CONFIG_SPD_EEPROM)
124 dram_size
= spd_sdram ();
126 dram_size
= fixed_sdram ();
132 #if defined(CONFIG_SYS_DRAM_TEST)
135 uint
*pstart
= (uint
*) 0x00000000;
136 uint
*pend
= (uint
*) 0x08000000;
139 for (p
= pstart
; p
< pend
; p
++)
142 for (p
= pstart
; p
< pend
; p
++) {
143 if (*p
!= 0xaaaaaaaa) {
144 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
149 for (p
= pstart
; p
< pend
; p
++)
152 for (p
= pstart
; p
< pend
; p
++) {
153 if (*p
!= 0x55555555) {
154 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
162 #if !defined(CONFIG_SPD_EEPROM)
163 /*************************************************************************
164 * fixed sdram init -- doesn't use serial presence detect.
166 * Assumes: 128 MB, non-ECC, non-registered
169 ************************************************************************/
170 long int fixed_sdram (void)
174 /*--------------------------------------------------------------------
176 *------------------------------------------------------------------*/
177 mtsdram (mem_uabba
, 0x00000000); /* ubba=0 (default) */
178 mtsdram (mem_slio
, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
179 mtsdram (mem_devopt
, 0x00000000); /* dll=0 ds=0 (normal) */
180 mtsdram (mem_wddctr
, 0x00000000); /* wrcp=0 dcd=0 */
181 mtsdram (mem_clktr
, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
183 /*--------------------------------------------------------------------
184 * Setup for board-specific specific mem
185 *------------------------------------------------------------------*/
187 * Following for CAS Latency = 2.5 @ 133 MHz PLB
189 mtsdram (mem_b0cr
, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
190 mtsdram (mem_tr0
, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
192 mtsdram (mem_tr1
, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
193 mtsdram (mem_rtr
, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
194 mtsdram (mem_cfg1
, 0x00000000); /* Self-refresh exit, disable PM */
195 udelay (400); /* Delay 200 usecs (min) */
197 /*--------------------------------------------------------------------
198 * Enable the controller, then wait for DCEN to complete
199 *------------------------------------------------------------------*/
200 mtsdram (mem_cfg0
, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
202 mfsdram (mem_mcsts
, reg
);
203 if (reg
& 0x80000000)
207 return (128 * 1024 * 1024); /* 128 MB */
209 #endif /* !defined(CONFIG_SPD_EEPROM) */
212 /*************************************************************************
215 * This routine is called just prior to registering the hose and gives
216 * the board the opportunity to check things. Returning a value of zero
217 * indicates that things are bad & PCI initialization should be aborted.
219 * Different boards may wish to customize the pci controller structure
220 * (add regions, override default access routines, etc) or perform
221 * certain pre-initialization actions.
223 ************************************************************************/
224 #if defined(CONFIG_PCI)
225 int pci_pre_init(struct pci_controller
* hose
)
228 /* See if we're supposed to setup the pci */
229 mfsdr(sdr_sdstp1
, strap
);
230 if ((strap
& 0x00010000) == 0) {
234 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
235 /* Setup System Device Register PCIX0_XCR */
236 mfsdr(sdr_xcr
, strap
);
238 mtsdr(sdr_xcr
, strap
);
242 #endif /* defined(CONFIG_PCI) */
244 /*************************************************************************
247 * The bootstrap configuration provides default settings for the pci
248 * inbound map (PIM). But the bootstrap config choices are limited and
249 * may not be sufficient for a given board.
251 ************************************************************************/
252 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
253 void pci_target_init(struct pci_controller
* hose
)
255 /*--------------------------------------------------------------------------+
257 *--------------------------------------------------------------------------*/
258 out32r( PCIX0_PIM0SA
, 0 ); /* disable */
259 out32r( PCIX0_PIM1SA
, 0 ); /* disable */
260 out32r( PCIX0_PIM2SA
, 0 ); /* disable */
261 out32r( PCIX0_EROMBA
, 0 ); /* disable expansion rom */
263 /*--------------------------------------------------------------------------+
264 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
265 * options to not support sizes such as 128/256 MB.
266 *--------------------------------------------------------------------------*/
267 out32r( PCIX0_PIM0LAL
, CONFIG_SYS_SDRAM_BASE
);
268 out32r( PCIX0_PIM0LAH
, 0 );
269 out32r( PCIX0_PIM0SA
, ~(gd
->ram_size
- 1) | 1 );
271 out32r( PCIX0_BAR0
, 0 );
273 /*--------------------------------------------------------------------------+
274 * Program the board's subsystem id/vendor id
275 *--------------------------------------------------------------------------*/
276 out16r( PCIX0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
277 out16r( PCIX0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
279 out16r( PCIX0_CMD
, in16r(PCIX0_CMD
) | PCI_COMMAND_MEMORY
);
281 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
284 /*************************************************************************
287 * This routine is called to determine if a pci scan should be
288 * performed. With various hardware environments (especially cPCI and
289 * PPMC) it's insufficient to depend on the state of the arbiter enable
290 * bit in the strap register, or generic host/adapter assumptions.
292 * Rather than hard-code a bad assumption in the general 440 code, the
293 * 440 pci code requires the board to decide at runtime.
295 * Return 0 for adapter mode, non-zero for host (monarch) mode.
298 ************************************************************************/
299 #if defined(CONFIG_PCI)
300 int is_pci_host(struct pci_controller
*hose
)
302 return ((in32(CONFIG_SYS_GPIO_BASE
+ 0x1C) & 0x00000800) == 0);
304 #endif /* defined(CONFIG_PCI) */
308 * Returns 1 if keys pressed to start the power-on long-running tests
309 * Called from board_init_f().
311 int post_hotkeys_pressed(void)
317 void post_word_store (ulong a
)
319 volatile ulong
*save_addr
=
320 (volatile ulong
*)(CONFIG_SYS_POST_WORD_ADDR
);
325 ulong
post_word_load (void)
327 volatile ulong
*save_addr
=
328 (volatile ulong
*)(CONFIG_SYS_POST_WORD_ADDR
);
334 /*-----------------------------------------------------------------------------
335 * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
336 *-----------------------------------------------------------------------------
338 static int enetaddr_num
= 0;
339 void board_get_enetaddr (uchar
* enet
)
342 unsigned char buff
[0x100], *cp
;
345 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
347 /* Read 256 bytes in EEPROM */
348 i2c_read (0x50, 0, 1, buff
, 0x100);
350 if (enetaddr_num
== 0) {
357 for (i
= 0; i
< 6; i
++,cp
++)
360 printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
361 enet
[0], enet
[1], enet
[2], enet
[3], enet
[4], enet
[5]);