board/xsengine/lowlevel_init.S

   1 #include <config.h>
   2 #include <version.h>
   3 #include <asm/arch/pxa-regs.h>
   4
   5 DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
   6
   7 .globl lowlevel_init
   8 lowlevel_init:
   9
  10    mov      r10, lr
  11
  12 /* ---- GPIO INITIALISATION ---- */
  13 /* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
  14
  15    /* General purpose set registers */
  16    ldr      r0,   =GPSR0
  17    ldr      r1,   =CONFIG_SYS_GPSR0_VAL
  18    str      r1,   [r0]
  19    ldr      r0,   =GPSR1
  20    ldr      r1,   =CONFIG_SYS_GPSR1_VAL
  21    str      r1,   [r0]
  22    ldr      r0,   =GPSR2
  23    ldr      r1,   =CONFIG_SYS_GPSR2_VAL
  24    str      r1,   [r0]
  25
  26    /* General purpose clear registers */
  27    ldr      r0,   =GPCR0
  28    ldr      r1,   =CONFIG_SYS_GPCR0_VAL
  29    str      r1,   [r0]
  30    ldr      r0,   =GPCR1
  31    ldr      r1,   =CONFIG_SYS_GPCR1_VAL
  32    str      r1,   [r0]
  33    ldr      r0,   =GPCR2
  34    ldr      r1,   =CONFIG_SYS_GPCR2_VAL
  35    str      r1,   [r0]
  36
  37    /* General rising edge registers */
  38    ldr      r0,   =GRER0
  39    ldr      r1,   =CONFIG_SYS_GRER0_VAL
  40    str      r1,   [r0]
  41    ldr      r0,   =GRER1
  42    ldr      r1,   =CONFIG_SYS_GRER1_VAL
  43    str      r1,   [r0]
  44    ldr      r0,   =GRER2
  45    ldr      r1,   =CONFIG_SYS_GRER2_VAL
  46    str      r1,   [r0]
  47
  48    /* General falling edge registers */
  49    ldr      r0,   =GFER0
  50    ldr      r1,   =CONFIG_SYS_GFER0_VAL
  51    str      r1,   [r0]
  52    ldr      r0,   =GFER1
  53    ldr      r1,   =CONFIG_SYS_GFER1_VAL
  54    str      r1,   [r0]
  55    ldr      r0,   =GFER2
  56    ldr      r1,   =CONFIG_SYS_GFER2_VAL
  57    str      r1,   [r0]
  58
  59    /* General edge detect registers */
  60    ldr      r0,   =GPDR0
  61    ldr      r1,   =CONFIG_SYS_GPDR0_VAL
  62    str      r1,   [r0]
  63    ldr      r0,   =GPDR1
  64    ldr      r1,   =CONFIG_SYS_GPDR1_VAL
  65    str      r1,   [r0]
  66    ldr      r0,   =GPDR2
  67    ldr      r1,   =CONFIG_SYS_GPDR2_VAL
  68    str      r1,   [r0]
  69
  70    /* General alternate function registers */
  71    ldr      r0,   =GAFR0_L              /* [0:15] */
  72    ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
  73    str      r1,   [r0]
  74    ldr      r0,   =GAFR0_U              /* [31:16] */
  75    ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
  76    str      r1,   [r0]
  77    ldr      r0,   =GAFR1_L              /* [47:32] */
  78    ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
  79    str      r1,   [r0]
  80    ldr      r0,   =GAFR1_U              /* [63:48] */
  81    ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
  82    str      r1,   [r0]
  83    ldr      r0,   =GAFR2_L              /* [79:64] */
  84    ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
  85    str      r1,   [r0]
  86    ldr      r0,   =GAFR2_U              /* [80] */
  87    ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
  88    str      r1,   [r0]
  89
  90    /* General purpose direction registers */
  91    ldr      r0,   =GPDR0
  92    ldr      r1,   =CONFIG_SYS_GPDR0_VAL
  93    str      r1,   [r0]
  94    ldr      r0,   =GPDR1
  95    ldr      r1,   =CONFIG_SYS_GPDR1_VAL
  96    str      r1,   [r0]
  97    ldr      r0,   =GPDR2
  98    ldr      r1,   =CONFIG_SYS_GPDR2_VAL
  99    str      r1,   [r0]
 100
 101    /* Power manager sleep status */
 102    ldr      r0,   =PSSR
 103    ldr      r1,   =CONFIG_SYS_PSSR_VAL
 104    str      r1,   [r0]
 105
 106 /* ---- MEMORY INITIALISATION ---- */
 107 /* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
 108 /* pause for 200 uSecs- allow internal clocks to settle */
 109    ldr r3, =OSCR        /* reset the OS Timer Count to zero */
 110    mov r2, #0
 111    str r2, [r3]
 112    ldr r4, =0x300       /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
 113 1:
 114    ldr r2, [r3]
 115    cmp r4, r2
 116    bgt 1b
 117
 118 mem_init:
 119 /* get memory controller base address */
 120    ldr     r1,  =MEMC_BASE
 121
 122 /* ---- FLASH INITIALISATION ---- */
 123 /* Write MSC0 and read back to ensure data change is accepted by cpu */
 124    ldr     r2,   =CONFIG_SYS_MSC0_VAL
 125    str     r2,   [r1, #MSC0_OFFSET]
 126    ldr     r2,   [r1, #MSC0_OFFSET]
 127
 128 /* ---- SDRAM INITIALISATION ---- */
 129 /* get the MDREFR settings */
 130    ldr     r2,  =CONFIG_SYS_MDREFR_VAL
 131    str     r2,  [r1, #MDREFR_OFFSET]
 132
 133 /* fetch platform value of MDCNFG */
 134    ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 135
 136 /* disable all sdram banks */
 137    bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
 138    bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
 139
 140 /* write initial value of MDCNFG, w/o enabling sdram banks */
 141    str     r2,  [r1, #MDCNFG_OFFSET]
 142
 143 /* pause for 200 uSecs */
 144    ldr r3, =OSCR        /* reset the OS Timer Count to zero */
 145    mov r2, #0
 146    str r2, [r3]
 147    ldr r4, =0x300       /* about 200 usec */
 148 1:
 149    ldr r2, [r3]
 150    cmp r4, r2
 151    bgt 1b
 152
 153 /* Access memory *not yet enabled* for CBR refresh cycles (8) */
 154 /* CBR is generated for all banks */
 155
 156    ldr     r2, =CONFIG_SYS_DRAM_BASE
 157    str     r2, [r2]
 158    str     r2, [r2]
 159    str     r2, [r2]
 160    str     r2, [r2]
 161    str     r2, [r2]
 162    str     r2, [r2]
 163    str     r2, [r2]
 164    str     r2, [r2]
 165
 166 /* get memory controller base address */
 167    ldr     r2,  =MEMC_BASE
 168
 169 /* Enable SDRAM bank 0 in MDCNFG register */
 170    ldr     r2,  [r1, #MDCNFG_OFFSET]
 171    orr     r2,  r2,  #MDCNFG_DE0
 172    str     r2,  [r1, #MDCNFG_OFFSET]
 173
 174 /* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
 175    ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 176    str     r2,  [r1, #MDMRS_OFFSET]
 177
 178 /* ---- INTERRUPT INITIALISATION ---- */
 179 /* Disable (mask) all interrupts at the interrupt controller */
 180 /* clear the interrupt level register (use IRQ, not FIQ) */
 181    mov     r1, #0
 182    ldr     r2,  =ICLR
 183    str     r1,  [r2]
 184
 185 /* Set interrupt mask register */
 186    ldr     r1,  =CONFIG_SYS_ICMR_VAL
 187    ldr     r2,  =ICMR
 188    str     r1,  [r2]
 189
 190 /* ---- CLOCK INITIALISATION ---- */
 191 /* Disable the peripheral clocks, and set the core clock */
 192
 193 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
 194    ldr     r1,  =CKEN
 195    mov     r2,  #0
 196    str     r2,  [r1]
 197
 198 /* set core clocks */
 199    ldr     r2,  =CONFIG_SYS_CCCR_VAL
 200    ldr     r1,  =CCCR
 201    str     r2,  [r1]
 202
 203 #ifdef ENABLE32KHZ
 204 /* enable the 32Khz oscillator for RTC and PowerManager */
 205    ldr     r1,  =OSCC
 206    mov     r2,  #OSCC_OON
 207    str     r2,  [r1]
 208
 209 /* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
 210 60:
 211    ldr     r2, [r1]
 212    ands    r2, r2, #1
 213    beq     60b
 214 #endif
 215
 216 /* Turn on needed clocks */
 217    ldr     r1,  =CKEN
 218    ldr     r2,  =CONFIG_SYS_CKEN_VAL
 219    str     r2,  [r1]
 220
 221    mov   pc, r10