board/zylonite/lowlevel_init.S

   1 /*
   2  * Most of this taken from Redboot hal_platform_setup.h with cleanup
   3  *
   4  * NOTE: I haven't clean this up considerably, just enough to get it
   5  * running. See hal_platform_setup.h for the source. See
   6  * board/cradle/lowlevel_init.S for another PXA250 setup that is
   7  * much cleaner.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <version.h>
  30 #include <asm/arch/pxa-regs.h>
  31
  32 DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
  33
  34 /* wait for coprocessor write complete */
  35 .macro CPWAIT reg
  36         mrc     p15,0,\reg,c2,c0,0
  37         mov     \reg,\reg
  38         sub     pc,pc,#4
  39 .endm
  40
  41
  42 .macro wait time
  43         ldr             r2, =OSCR
  44         mov             r3, #0
  45         str             r3, [r2]
  46 0:
  47         ldr             r3, [r2]
  48         cmp             r3, \time
  49         bls             0b
  50 .endm
  51
  52 /*
  53  *      Memory setup
  54  */
  55
  56 .globl lowlevel_init
  57 lowlevel_init:
  58         /* Set up GPIO pins first ----------------------------------------- */
  59         mov      r10, lr
  60
  61         /*  Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
  62         ldr             r0, =0x40E10438 @ GPIO41 FFRXD
  63         ldr             r1, =0x802
  64         str             r1, [r0]
  65
  66         ldr             r0, =0x40E1043C @ GPIO42 FFTXD
  67         ldr             r1, =0x802
  68         str             r1, [r0]
  69
  70         ldr             r0, =0x40E10440 @ GPIO43 FFCTS
  71         ldr             r1, =0x802
  72         str             r1, [r0]
  73
  74         ldr             r0, =0x40E10444 @ GPIO 44 FFDCD
  75         ldr             r1, =0x802
  76         str             r1, [r0]
  77
  78         ldr             r0, =0x40E10448 @ GPIO 45 FFDSR
  79         ldr             r1, =0x802
  80         str             r1, [r0]
  81
  82         ldr             r0, =0x40E1044C @ GPIO 46 FFRI
  83         ldr             r1, =0x802
  84         str             r1, [r0]
  85
  86         ldr             r0, =0x40E10450 @ GPIO 47 FFDTR
  87         ldr             r1, =0x802
  88         str             r1, [r0]
  89
  90         ldr             r0, =0x40E10454 @ GPIO 48
  91         ldr             r1, =0x802
  92         str             r1, [r0]
  93
  94         /* tebrandt - ASCR, clear the RDH bit */
  95         ldr             r0, =ASCR
  96         ldr             r1, [r0]
  97         bic             r1, r1, #0x80000000
  98         str             r1, [r0]
  99
 100         /* ---------------------------------------------------------------- */
 101         /* Enable memory interface                                          */
 102         /*                                                                  */
 103         /* The sequence below is based on the recommended init steps        */
 104         /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
 105         /* Chapter 10.                                                      */
 106         /* ---------------------------------------------------------------- */
 107
 108         /* ---------------------------------------------------------------- */
 109         /* Step 1: Wait for at least 200 microsedonds to allow internal     */
 110         /*         clocks to settle. Only necessary after hard reset...     */
 111         /*         FIXME: can be optimized later                            */
 112         /* ---------------------------------------------------------------- */
 113
 114         /* mk:   replaced with wait macro */
 115 /*      ldr r3, =OSCR                   /\* reset the OS Timer Count to zero *\/ */
 116 /*      mov r2, #0 */
 117 /*      str r2, [r3] */
 118 /*      ldr r4, =0x300                  /\* really 0x2E1 is about 200usec,   *\/ */
 119 /*                                      /\* so 0x300 should be plenty        *\/ */
 120 /* 1: */
 121 /*      ldr r2, [r3] */
 122 /*      cmp r4, r2 */
 123 /*      bgt 1b */
 124         wait #300
 125
 126 mem_init:
 127
 128         /* configure the MEMCLKCFG register */
 129         ldr             r1, =MEMCLKCFG
 130         ldr             r2, =0x00010001
 131         str             r2, [r1]             @ WRITE
 132         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 133
 134         /* set CSADRCFG[0] to data flash SRAM mode */
 135         ldr             r1, =CSADRCFG0
 136         ldr             r2, =0x00320809
 137         str             r2, [r1]             @ WRITE
 138         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 139
 140         /* set CSADRCFG[1] to data flash SRAM mode */
 141         ldr             r1, =CSADRCFG1
 142         ldr             r2, =0x00320809
 143         str             r2, [r1]             @ WRITE
 144         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 145
 146         /* set MSC 0 register for SRAM memory */
 147         ldr             r1, =MSC0
 148         ldr             r2, =0x11191119
 149         str             r2, [r1]             @ WRITE
 150         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 151
 152         /* set CSADRCFG[2] to data flash SRAM mode */
 153         ldr             r1, =CSADRCFG2
 154         ldr             r2, =0x00320809
 155         str             r2, [r1]             @ WRITE
 156         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 157
 158         /* set CSADRCFG[3] to VLIO mode */
 159         ldr             r1, =CSADRCFG3
 160         ldr             r2, =0x0032080B
 161         str             r2, [r1]             @ WRITE
 162         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 163
 164         /* set MSC 1 register for VLIO memory */
 165         ldr             r1, =MSC1
 166         ldr             r2, =0x123C1119
 167         str             r2, [r1]             @ WRITE
 168         ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
 169
 170 #if 0
 171         /* This does not work in Zylonite. -SC */
 172         ldr             r0, =0x15fffff0
 173         ldr             r1, =0xb10b
 174         str             r1, [r0]
 175         str             r1, [r0, #4]
 176 #endif
 177
 178         /* Configure ACCR Register */
 179         ldr             r0, =ACCR               @ ACCR
 180         ldr             r1, =0x0180b108
 181         str             r1, [r0]
 182         ldr             r1, [r0]
 183
 184         /* Configure MDCNFG Register */
 185         ldr             r0, =MDCNFG             @ MDCNFG
 186         ldr             r1, =0x403
 187         str             r1, [r0]
 188         ldr             r1, [r0]
 189
 190         /* Perform Resistive Compensation by configuring RCOMP register */
 191         ldr             r1, =RCOMP              @ RCOMP
 192         ldr             r2, =0x000000ff
 193         str             r2, [r1]
 194         ldr             r2, [r1]
 195
 196         /* Configure MDMRS Register for SDCS0 */
 197         ldr             r1, =MDMRS              @ MDMRS
 198         ldr             r2, =0x60000023
 199         ldr             r3, [r1]
 200         orr             r2, r2, r3
 201         str             r2, [r1]
 202         ldr             r2, [r1]
 203
 204         /* Configure MDMRS Register for SDCS1 */
 205         ldr             r1, =MDMRS              @ MDMRS
 206         ldr             r2, =0xa0000023
 207         ldr             r3, [r1]
 208         orr             r2, r2, r3
 209         str             r2, [r1]
 210         ldr             r2, [r1]
 211
 212         /* Configure MDREFR */
 213         ldr             r1, =MDREFR             @ MDREFR
 214         ldr             r2, =0x00000006
 215         str             r2, [r1]
 216         ldr             r2, [r1]
 217
 218         /* Configure EMPI */
 219         ldr             r1, =EMPI               @ EMPI
 220         ldr             r2, =0x80000000
 221         str             r2, [r1]
 222         ldr             r2, [r1]
 223
 224         /* Hardware DDR Read-Strobe Delay Calibration */
 225         ldr             r0, =DDR_HCAL           @ DDR_HCAL
 226         ldr             r1, =0x803ffc07     @ the offset is correct? -SC
 227         str             r1, [r0]
 228         wait            #5
 229         ldr             r1, [r0]
 230
 231         /* Here we assume the hardware calibration alwasy be successful. -SC */
 232         /* Set DMCEN bit in MDCNFG Register */
 233         ldr             r0, =MDCNFG             @ MDCNFG
 234         ldr             r1, [r0]
 235         orr             r1, r1, #0x40000000     @ enable SDRAM for Normal Access
 236         str             r1, [r0]
 237
 238 #ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
 239         /* scrub/init SDRAM if enabled/present */
 240 /*      ldr     r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
 241 /*      ldr     r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
 242 /*      mov     r8,r12           /\* save DRAM size (mk: why???) *\/ */
 243         ldr     r8, =0xa0000000  /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
 244         ldr     r9, =0x04000000  /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
 245         mov     r0, #0           /* scrub with 0x0000:0000 */
 246         mov     r1, #0
 247         mov     r2, #0
 248         mov     r3, #0
 249         mov     r4, #0
 250         mov     r5, #0
 251         mov     r6, #0
 252         mov     r7, #0
 253 10:     /* fastScrubLoop */
 254         subs    r9, r9, #32     /* 32 bytes/line */
 255         stmia   r8!, {r0-r7}
 256         beq     15f
 257         b       10b
 258 #endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
 259
 260 15:
 261         /* Mask all interrupts */
 262         mov     r1, #0
 263         mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 264
 265         /* Disable software and data breakpoints */
 266         mov     r0, #0
 267         mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
 268         mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
 269         mcr     p15,0,r0,c14,c4,0  /* dbcon */
 270
 271         /* Enable all debug functionality */
 272         mov     r0,#0x80000000
 273         mcr     p14,0,r0,c10,c0,0  /* dcsr */
 274
 275         /* We are finished with Intel's memory controller initialisation    */
 276
 277         /* ---------------------------------------------------------------- */
 278         /* End lowlevel_init                                                     */
 279         /* ---------------------------------------------------------------- */
 280
 281 endlowlevel_init:
 282
 283         mov     pc, lr
 284
 285 /*
 286 @********************************************************************************
 287 @ DDR calibration
 288 @
 289 @  This function is used to calibrate DQS delay lines.
 290 @ Monahans supports three ways to do it. One is software
 291 @ calibration. Two is hardware calibration. Three is hybrid
 292 @ calibration.
 293 @
 294 @ TBD
 295 @ -SC
 296 ddr_calibration:
 297
 298         @ Case 1:       Write the correct delay value once
 299         @ Configure DDR_SCAL Register
 300         ldr     r0, =DDR_SCAL           @ DDR_SCAL
 301 q       ldr     r1, =0xaf2f2f2f
 302         str     r1, [r0]
 303         ldr     r1, [r0]
 304 */
 305 /*      @ Case 2:       Software Calibration
 306         @ Write test pattern to memory
 307         ldr     r5, =0x0faf0faf         @ Data Pattern
 308         ldr     r4, =0xa0000000         @ DDR ram
 309         str     r5, [r4]
 310
 311         mov     r1, =0x0                @ delay count
 312         mov     r6, =0x0
 313         mov     r7, =0x0
 314 ddr_loop1:
 315         add     r1, r1, =0x1
 316         cmp     r1, =0xf
 317         ble     end_loop
 318         mov     r3, r1
 319         mov     r0, r1, lsl #30
 320         orr     r3, r3, r0
 321         mov     r0, r1, lsl #22
 322         orr     r3, r3, r0
 323         mov     r0, r1, lsl #14
 324         orr     r3, r3, r0
 325         orr     r3, r3, =0x80000000
 326         ldr     r2, =DDR_SCAL
 327         str     r3, [r2]
 328
 329         ldr     r2, [r4]
 330         cmp     r2, r5
 331         bne     ddr_loop1
 332         mov     r6, r1
 333 ddr_loop2:
 334         add     r1, r1, =0x1
 335         cmp     r1, =0xf
 336         ble     end_loop
 337         mov     r3, r1
 338         mov     r0, r1, lsl #30
 339         orr     r3, r3, r0
 340         mov     r0, r1, lsl #22
 341         orr     r3, r3, r0
 342         mov     r0, r1, lsl #14
 343         orr     r3, r3, r0
 344         orr     r3, r3, =0x80000000
 345         ldr     r2, =DDR_SCAL
 346         str     r3, [r2]
 347
 348         ldr     r2, [r4]
 349         cmp     r2, r5
 350         be      ddr_loop2
 351         mov     r7, r2
 352
 353         add     r3, r6, r7
 354         lsr     r3, r3, =0x1
 355         mov     r0, r1, lsl #30
 356         orr     r3, r3, r0
 357         mov     r0, r1, lsl #22
 358         orr     r3, r3, r0
 359         mov     r0, r1, lsl #14
 360         orr     r3, r3, r0
 361         orr     r3, r3, =0x80000000
 362         ldr     r2, =DDR_SCAL
 363
 364 end_loop:
 365
 366         @ Case 3:       Hardware Calibratoin
 367         ldr     r0, =DDR_HCAL           @ DDR_HCAL
 368         ldr     r1, =0x803ffc07     @ the offset is correct? -SC
 369         str     r1, [r0]
 370         wait    #5
 371         ldr     r1, [r0]
 372         mov     pc, lr
 373 */