3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <common.h> /* core U-Boot definitions */
29 #include <ACEX1K.h> /* ACEX device family */
31 /* Define FPGA_DEBUG to get debug printf's */
33 #define PRINTF(fmt,args...) printf (fmt ,##args)
35 #define PRINTF(fmt,args...)
38 /* Note: The assumption is that we cannot possibly run fast enough to
39 * overrun the device (the Slave Parallel mode can free run at 50MHz).
40 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
41 * the board config file to slow things down.
43 #ifndef CONFIG_FPGA_DELAY
44 #define CONFIG_FPGA_DELAY()
47 #ifndef CONFIG_SYS_FPGA_WAIT
48 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
51 static int ACEX1K_ps_load( Altera_desc
*desc
, void *buf
, size_t bsize
);
52 static int ACEX1K_ps_dump( Altera_desc
*desc
, void *buf
, size_t bsize
);
53 /* static int ACEX1K_ps_info( Altera_desc *desc ); */
54 static int ACEX1K_ps_reloc( Altera_desc
*desc
, ulong reloc_offset
);
56 /* ------------------------------------------------------------------------- */
57 /* ACEX1K Generic Implementation */
58 int ACEX1K_load (Altera_desc
* desc
, void *buf
, size_t bsize
)
60 int ret_val
= FPGA_FAIL
;
62 switch (desc
->iface
) {
64 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__
);
65 ret_val
= ACEX1K_ps_load (desc
, buf
, bsize
);
68 /* Add new interface types here */
71 printf ("%s: Unsupported interface type, %d\n",
72 __FUNCTION__
, desc
->iface
);
78 int ACEX1K_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
80 int ret_val
= FPGA_FAIL
;
82 switch (desc
->iface
) {
84 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__
);
85 ret_val
= ACEX1K_ps_dump (desc
, buf
, bsize
);
88 /* Add new interface types here */
91 printf ("%s: Unsupported interface type, %d\n",
92 __FUNCTION__
, desc
->iface
);
98 int ACEX1K_info( Altera_desc
*desc
)
104 int ACEX1K_reloc (Altera_desc
* desc
, ulong reloc_offset
)
106 int ret_val
= FPGA_FAIL
; /* assume a failure */
108 if (desc
->family
!= Altera_ACEX1K
) {
109 printf ("%s: Unsupported family type, %d\n",
110 __FUNCTION__
, desc
->family
);
113 switch (desc
->iface
) {
115 ret_val
= ACEX1K_ps_reloc (desc
, reloc_offset
);
118 /* Add new interface types here */
121 printf ("%s: Unsupported interface type, %d\n",
122 __FUNCTION__
, desc
->iface
);
129 /* ------------------------------------------------------------------------- */
130 /* ACEX1K Passive Serial Generic Implementation */
132 static int ACEX1K_ps_load (Altera_desc
* desc
, void *buf
, size_t bsize
)
134 int ret_val
= FPGA_FAIL
; /* assume the worst */
135 Altera_ACEX1K_Passive_Serial_fns
*fn
= desc
->iface_fns
;
138 PRINTF ("%s: start with interface functions @ 0x%p\n",
142 size_t bytecount
= 0;
143 unsigned char *data
= (unsigned char *) buf
;
144 int cookie
= desc
->cookie
; /* make a local copy */
145 unsigned long ts
; /* timestamp */
147 PRINTF ("%s: Function Table:\n"
155 __FUNCTION__
, &fn
, fn
, fn
->config
, fn
->status
,
156 fn
->clk
, fn
->data
, fn
->done
);
157 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
158 printf ("Loading FPGA Device %d...", cookie
);
162 * Run the pre configuration function if there is one.
168 /* Establish the initial state */
169 (*fn
->config
) (TRUE
, TRUE
, cookie
); /* Assert nCONFIG */
171 udelay(2); /* T_cfg > 2us */
173 /* nSTATUS should be asserted now */
174 (*fn
->done
) (cookie
);
175 if ( !(*fn
->status
) (cookie
) ) {
176 puts ("** nSTATUS is not asserted.\n");
177 (*fn
->abort
) (cookie
);
181 (*fn
->config
) (FALSE
, TRUE
, cookie
); /* Deassert nCONFIG */
182 udelay(2); /* T_cf2st1 < 4us */
184 /* Wait for nSTATUS to be released (i.e. deasserted) */
185 ts
= get_timer (0); /* get current time */
187 CONFIG_FPGA_DELAY ();
188 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
189 puts ("** Timeout waiting for STATUS to go high.\n");
190 (*fn
->abort
) (cookie
);
193 (*fn
->done
) (cookie
);
194 } while ((*fn
->status
) (cookie
));
196 /* Get ready for the burn */
197 CONFIG_FPGA_DELAY ();
200 while (bytecount
< bsize
) {
202 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
204 (*fn
->abort
) (cookie
);
208 /* Altera detects an error if INIT goes low (active)
209 while DONE is low (inactive) */
210 #if 0 /* not yet implemented */
211 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
212 puts ("** CRC error during FPGA load.\n");
213 (*fn
->abort
) (cookie
);
217 val
= data
[bytecount
++ ];
220 /* Deassert the clock */
221 (*fn
->clk
) (FALSE
, TRUE
, cookie
);
222 CONFIG_FPGA_DELAY ();
224 (*fn
->data
) ( (val
& 0x01), TRUE
, cookie
);
225 CONFIG_FPGA_DELAY ();
226 /* Assert the clock */
227 (*fn
->clk
) (TRUE
, TRUE
, cookie
);
228 CONFIG_FPGA_DELAY ();
233 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
234 if (bytecount
% (bsize
/ 40) == 0)
235 putc ('.'); /* let them know we are alive */
239 CONFIG_FPGA_DELAY ();
241 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
242 putc (' '); /* terminate the dotted line */
246 * Checking FPGA's CONF_DONE signal - correctly booted ?
249 if ( ! (*fn
->done
) (cookie
) ) {
250 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
251 (*fn
->abort
) (cookie
);
256 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
259 for (i
= 0; i
< 12; i
++) {
260 CONFIG_FPGA_DELAY ();
261 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
262 CONFIG_FPGA_DELAY ();
263 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
266 ret_val
= FPGA_SUCCESS
;
268 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
269 if (ret_val
== FPGA_SUCCESS
) {
276 (*fn
->post
) (cookie
);
279 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
285 static int ACEX1K_ps_dump (Altera_desc
* desc
, void *buf
, size_t bsize
)
287 /* Readback is only available through the Slave Parallel and */
288 /* boundary-scan interfaces. */
289 printf ("%s: Passive Serial Dumping is unavailable\n",
294 static int ACEX1K_ps_reloc (Altera_desc
* desc
, ulong reloc_offset
)
296 int ret_val
= FPGA_FAIL
; /* assume the worst */
297 Altera_ACEX1K_Passive_Serial_fns
*fn_r
, *fn
=
298 (Altera_ACEX1K_Passive_Serial_fns
*) (desc
->iface_fns
);
303 /* Get the relocated table address */
304 addr
= (ulong
) fn
+ reloc_offset
;
305 fn_r
= (Altera_ACEX1K_Passive_Serial_fns
*) addr
;
307 if (!fn_r
->relocated
) {
309 if (memcmp (fn_r
, fn
,
310 sizeof (Altera_ACEX1K_Passive_Serial_fns
))
312 /* good copy of the table, fix the descriptor pointer */
313 desc
->iface_fns
= fn_r
;
315 PRINTF ("%s: Invalid function table at 0x%p\n",
320 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__
,
323 addr
= (ulong
) (fn
->pre
) + reloc_offset
;
324 fn_r
->pre
= (Altera_pre_fn
) addr
;
326 addr
= (ulong
) (fn
->config
) + reloc_offset
;
327 fn_r
->config
= (Altera_config_fn
) addr
;
329 addr
= (ulong
) (fn
->status
) + reloc_offset
;
330 fn_r
->status
= (Altera_status_fn
) addr
;
332 addr
= (ulong
) (fn
->done
) + reloc_offset
;
333 fn_r
->done
= (Altera_done_fn
) addr
;
335 addr
= (ulong
) (fn
->clk
) + reloc_offset
;
336 fn_r
->clk
= (Altera_clk_fn
) addr
;
338 addr
= (ulong
) (fn
->data
) + reloc_offset
;
339 fn_r
->data
= (Altera_data_fn
) addr
;
341 addr
= (ulong
) (fn
->abort
) + reloc_offset
;
342 fn_r
->abort
= (Altera_abort_fn
) addr
;
344 addr
= (ulong
) (fn
->post
) + reloc_offset
;
345 fn_r
->post
= (Altera_post_fn
) addr
;
347 fn_r
->relocated
= TRUE
;
350 /* this table has already been moved */
351 /* XXX - should check to see if the descriptor is correct */
352 desc
->iface_fns
= fn_r
;
355 ret_val
= FPGA_SUCCESS
;
357 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);