]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/arm1136/cpu.c
2 * (C) Copyright 2004 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 DECLARE_GLOBAL_DATA_PTR
;
41 /* read co-processor 15, register #1 (control register) */
42 static unsigned long read_p15_c1 (void)
47 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
54 /* write to co-processor 15, register #1 (control register) */
55 static void write_p15_c1 (unsigned long value
)
58 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
66 static void cp_delay (void)
70 /* Many OMAP regs need at least 2 nops */
71 for (i
= 0; i
< 100; i
++);
74 /* See also ARM Ref. Man. */
75 #define C1_MMU (1<<0) /* mmu off/on */
76 #define C1_ALIGN (1<<1) /* alignment faults off/on */
77 #define C1_DC (1<<2) /* dcache off/on */
78 #define C1_WB (1<<3) /* merging write buffer on/off */
79 #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
80 #define C1_SYS_PROT (1<<8) /* system protection */
81 #define C1_ROM_PROT (1<<9) /* ROM protection */
82 #define C1_IC (1<<12) /* icache off/on */
83 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
84 #define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
89 * setup up stacks if necessary
92 IRQ_STACK_START
= _armboot_start
- CONFIG_SYS_MALLOC_LEN
- CONFIG_SYS_GBL_DATA_SIZE
- 4;
93 FIQ_STACK_START
= IRQ_STACK_START
- CONFIG_STACKSIZE_IRQ
;
98 int cleanup_before_linux (void)
101 * this function is called just before we call linux
102 * it prepares the processor for linux
104 * we turn off caches etc ...
109 disable_interrupts ();
113 extern void lcd_disable(void);
114 extern void lcd_panel_disable(void);
116 lcd_disable(); /* proper disable of lcd & panel */
121 /* turn off I/D-cache */
122 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i
));
123 i
&= ~(C1_DC
| C1_IC
);
124 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i
));
126 /* flush I/D-cache */
128 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i
)); /* invalidate both caches and flush btb */
129 asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i
)); /* mem barrier to sync things */
133 int do_reset (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
135 disable_interrupts ();
141 void icache_enable (void)
145 reg
= read_p15_c1 (); /* get control reg. */
147 write_p15_c1 (reg
| C1_IC
);
150 void icache_disable (void)
154 reg
= read_p15_c1 ();
156 write_p15_c1 (reg
& ~C1_IC
);
159 int icache_status (void)
161 return(read_p15_c1 () & C1_IC
) != 0;