]> git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/arm1136/cpu.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / cpu / arm1136 / cpu.c
1 /*
2 * (C) Copyright 2004 Texas Insturments
3 *
4 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * (C) Copyright 2002
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30 /*
31 * CPU specific code
32 */
33
34 #include <common.h>
35 #include <command.h>
36
37 #ifdef CONFIG_USE_IRQ
38 DECLARE_GLOBAL_DATA_PTR;
39 #endif
40
41 /* read co-processor 15, register #1 (control register) */
42 static unsigned long read_p15_c1 (void)
43 {
44 unsigned long value;
45
46 __asm__ __volatile__(
47 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
48 : "=r" (value)
49 :
50 : "memory");
51 return value;
52 }
53
54 /* write to co-processor 15, register #1 (control register) */
55 static void write_p15_c1 (unsigned long value)
56 {
57 __asm__ __volatile__(
58 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
59 :
60 : "r" (value)
61 : "memory");
62
63 read_p15_c1 ();
64 }
65
66 static void cp_delay (void)
67 {
68 volatile int i;
69
70 /* Many OMAP regs need at least 2 nops */
71 for (i = 0; i < 100; i++);
72 }
73
74 /* See also ARM Ref. Man. */
75 #define C1_MMU (1<<0) /* mmu off/on */
76 #define C1_ALIGN (1<<1) /* alignment faults off/on */
77 #define C1_DC (1<<2) /* dcache off/on */
78 #define C1_WB (1<<3) /* merging write buffer on/off */
79 #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
80 #define C1_SYS_PROT (1<<8) /* system protection */
81 #define C1_ROM_PROT (1<<9) /* ROM protection */
82 #define C1_IC (1<<12) /* icache off/on */
83 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
84 #define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
85
86 int cpu_init (void)
87 {
88 /*
89 * setup up stacks if necessary
90 */
91 #ifdef CONFIG_USE_IRQ
92 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
93 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
94 #endif
95 return 0;
96 }
97
98 int cleanup_before_linux (void)
99 {
100 /*
101 * this function is called just before we call linux
102 * it prepares the processor for linux
103 *
104 * we turn off caches etc ...
105 */
106
107 unsigned long i;
108
109 disable_interrupts ();
110
111 #ifdef CONFIG_LCD
112 {
113 extern void lcd_disable(void);
114 extern void lcd_panel_disable(void);
115
116 lcd_disable(); /* proper disable of lcd & panel */
117 lcd_panel_disable();
118 }
119 #endif
120
121 /* turn off I/D-cache */
122 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
123 i &= ~(C1_DC | C1_IC);
124 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
125
126 /* flush I/D-cache */
127 i = 0;
128 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
129 asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
130 return(0);
131 }
132
133 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
134 {
135 disable_interrupts ();
136 reset_cpu (0);
137 /*NOTREACHED*/
138 return(0);
139 }
140
141 void icache_enable (void)
142 {
143 ulong reg;
144
145 reg = read_p15_c1 (); /* get control reg. */
146 cp_delay ();
147 write_p15_c1 (reg | C1_IC);
148 }
149
150 void icache_disable (void)
151 {
152 ulong reg;
153
154 reg = read_p15_c1 ();
155 cp_delay ();
156 write_p15_c1 (reg & ~C1_IC);
157 }
158
159 int icache_status (void)
160 {
161 return(read_p15_c1 () & C1_IC) != 0;
162 }