2 * Copyright (C) 2005-2008 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/ptrace.h>
24 #include <asm/sysreg.h>
26 #define SYSREG_MMUCR_I_OFFSET 2
27 #define SYSREG_MMUCR_S_OFFSET 4
29 #define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
30 #define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
31 | SYSREG_BIT(FE) | SYSREG_BIT(RE) \
32 | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
35 * To save some space, we use the same entry point for
36 * exceptions and reset. This avoids lots of alignment padding
37 * since the reset vector is always suitably aligned.
39 .section .exception.text, "ax", @progbits
42 .type _start, @function
43 .type _evba, @function
48 rjmp unknown_exception /* Unrecoverable exception */
50 rjmp unknown_exception /* TLB multiple hit */
52 rjmp unknown_exception /* Bus error data fetch */
54 rjmp unknown_exception /* Bus error instruction fetch */
56 rjmp unknown_exception /* NMI */
58 rjmp unknown_exception /* Instruction address */
60 rjmp unknown_exception /* ITLB protection */
62 rjmp unknown_exception /* Breakpoint */
64 rjmp unknown_exception /* Illegal opcode */
66 rjmp unknown_exception /* Unimplemented instruction */
68 rjmp unknown_exception /* Privilege violation */
70 rjmp unknown_exception /* Floating-point */
72 rjmp unknown_exception /* Coprocessor absent */
74 rjmp unknown_exception /* Data Address (read) */
76 rjmp unknown_exception /* Data Address (write) */
78 rjmp unknown_exception /* DTLB Protection (read) */
80 rjmp unknown_exception /* DTLB Protection (write) */
82 rjmp unknown_exception /* DTLB Modified */
85 rjmp unknown_exception /* ITLB Miss */
87 rjmp unknown_exception /* DTLB Miss (read) */
89 rjmp unknown_exception /* DTLB Miss (write) */
91 .size _evba, . - _evba
94 .type unknown_exception, @function
96 /* Figure out whether we're handling an exception (Exception
97 * mode) or just booting (Supervisor mode). */
98 csrfcz SYSREG_M1_OFFSET
99 brcc at32ap_cpu_bootstrap
101 /* This is an exception. Complain. */
103 sub r8, sp, REG_R12 - REG_R0 - 4
105 mfsr r10, SYSREG_RAR_EX
106 mfsr r11, SYSREG_RSR_EX
110 rcall do_unknown_exception
113 /* The COUNT/COMPARE timer interrupt handler */
114 .global timer_interrupt_handler
115 .type timer_interrupt_handler,@function
117 timer_interrupt_handler:
119 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
121 * We're running at interrupt level 3, so we don't need to save
122 * r8-r12 or lr to the stack.
124 lda.w r8, timer_overflow
127 mtsr SYSREG_COMPARE, r10
133 * CPU bootstrap after reset is handled here. SoC code may
134 * override this in case they need to initialize oscillators,
137 .section .text.at32ap_cpu_bootstrap, "ax", @progbits
138 .global at32ap_cpu_bootstrap
139 .weak at32ap_cpu_bootstrap
140 .type at32ap_cpu_bootstrap, @function
142 at32ap_cpu_bootstrap:
143 /* Reset the Status Register */
148 /* Reset CPUCR and invalidate the BTB */
150 mtsr SYSREG_CPUCR, r2
152 /* Flush the caches */
158 /* Reset the MMU to default settings */
159 mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
160 mtsr SYSREG_MMUCR, r0
162 /* Internal RAM should not need any initialization. We might
163 have to initialize external RAM here if the part doesn't
164 have internal RAM (or we may use the data cache) */
166 /* Jump to cacheable segment */
170 1: .long at32ap_low_level_init
171 .size _start, . - _start
173 /* Common CPU bootstrap code after oscillator/cache/etc. init */
174 .section .text.avr32ap_low_level_init, "ax", @progbits
175 .global at32ap_low_level_init
176 .type at32ap_low_level_init, @function
178 at32ap_low_level_init:
181 /* Initialize the GOT pointer */
189 .type sp_init,@object
191 .long CONFIG_SYS_INIT_SP_ADDR
193 .long 3b - _GLOBAL_OFFSET_TABLE_
196 * void relocate_code(new_sp, new_gd, monitor_addr)
198 * Relocate the u-boot image into RAM and continue from there.
201 .section .text.relocate_code,"ax",@progbits
202 .global relocate_code
203 .type relocate_code,@function
205 mov sp, r12 /* use new stack */
206 mov r12, r11 /* save new_gd */
207 mov r11, r10 /* save destination address */
209 /* copy .text section and flush the cache along the way */
212 sub lr, r10, r8 /* relocation offset */
221 cache r10[-4], 0x0d /* dcache clean/invalidate */
222 cache r10[-4], 0x01 /* icache invalidate */
225 /* flush write buffer */
228 /* copy data sections */
245 sub r0, pc, . - in_ram
250 /* find the new GOT and relocate it */
251 lddpc r6, got_init_reloc
263 /* Move the exception handlers */
268 /* Do the rest of the initialization sequence */
273 .long 3b - _GLOBAL_OFFSET_TABLE_
275 .size relocate_code, . - relocate_code