cpu/at32ap/start.S

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #include <config.h>
  23 #include <asm/sysreg.h>
  24
  25 #ifndef PART_SPECIFIC_BOOTSTRAP
  26 # define PART_SPECIFIC_BOOTSTRAP
  27 #endif
  28
  29 #define SYSREG_MMUCR_I_OFFSET   2
  30 #define SYSREG_MMUCR_S_OFFSET   4
  31
  32 #define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
  33 #define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE)             \
  34                     | SYSREG_BIT(FE) | SYSREG_BIT(RE)           \
  35                     | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
  36
  37         .text
  38         .global _start
  39 _start:
  40         PART_SPECIFIC_BOOTSTRAP
  41
  42         /* Reset the Status Register */
  43         mov     r0, lo(SR_INIT)
  44         orh     r0, hi(SR_INIT)
  45         mtsr    SYSREG_SR, r0
  46
  47         /* Reset CPUCR and invalidate the BTB */
  48         mov     r2, CPUCR_INIT
  49         mtsr    SYSREG_CPUCR, r2
  50
  51         /* Flush the caches */
  52         mov     r1, 0
  53         cache   r1[4], 8
  54         cache   r1[0], 0
  55         sync    0
  56
  57         /* Reset the MMU to default settings */
  58         mov     r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
  59         mtsr    SYSREG_MMUCR, r0
  60
  61         /* Internal RAM should not need any initialization.  We might
  62            have to initialize external RAM here if the part doesn't
  63            have internal RAM (or we may use the data cache) */
  64
  65         /* Jump to cacheable segment */
  66         lddpc   pc, 1f
  67
  68         .align  2
  69 1:      .long   2f
  70
  71 2:      lddpc   sp, sp_init
  72
  73         /*
  74          * Relocate the data section and initialize .bss.  Everything
  75          * is guaranteed to be at least doubleword aligned by the
  76          * linker script.
  77          */
  78         lddpc   r12, .Ldata_vma
  79         lddpc   r11, .Ldata_lma
  80         lddpc   r10, .Ldata_end
  81         sub     r10, r12
  82 4:      ld.d    r8, r11++
  83         sub     r10, 8
  84         st.d    r12++, r8
  85         brne    4b
  86
  87         mov     r8, 0
  88         mov     r9, 0
  89         lddpc   r10, .Lbss_end
  90         sub     r10, r12
  91 4:      sub     r10, 8
  92         st.d    r12++, r8
  93         brne    4b
  94
  95         /* Initialize the GOT pointer */
  96         lddpc   r6, got_init
  97 3:      rsub    r6, pc
  98         ld.w    pc, r6[board_init_f@got]
  99
 100         .align  2
 101         .type   sp_init,@object
 102 sp_init:
 103         .long   CFG_INIT_SP_ADDR
 104 got_init:
 105         .long   3b - _GLOBAL_OFFSET_TABLE_
 106 .Ldata_lma:
 107         .long   __data_lma
 108 .Ldata_vma:
 109         .long   _data
 110 .Ldata_end:
 111         .long   _edata
 112 .Lbss_end:
 113         .long   _end