3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/i8259.h>
28 #include <asm/ibmpc.h>
37 } __attribute__ ((packed
));
40 struct idt_entry idt
[256];
45 typedef struct irq_handler
{
46 struct irq_handler
*next
;
47 interrupt_handler_t
* isr_func
;
51 #define IRQ_DISABLED 1
54 irq_handler_t
*handler
;
58 static irq_desc_t irq_table
[MAX_IRQ
];
71 char exception_stack
[4096];
73 #define DECLARE_INTERRUPT(x) \
74 asm(".globl irq_"#x"\n" \
78 "pushl $irq_return\n" \
80 void __attribute__ ((regparm(0))) irq_##x(void)
82 #define DECLARE_EXCEPTION(x, f) \
83 asm(".globl exp_"#x"\n" \
87 "movl $exception_stack, %eax\n" \
88 "movl %eax, %esp \n" \
90 "movl 32(%esp), %ebx\n" \
92 "movw 36(%esp), %dx\n" \
96 "pushl $exp_return\n" \
98 void __attribute__ ((regparm(0))) exp_##x(void)
100 DECLARE_EXCEPTION(0, divide_exception_entry
); /* Divide exception */
101 DECLARE_EXCEPTION(1, debug_exception_entry
); /* Debug exception */
102 DECLARE_EXCEPTION(2, nmi_entry
); /* NMI */
103 DECLARE_EXCEPTION(3, unknown_exception_entry
); /* Breakpoint/Coprocessor Error */
104 DECLARE_EXCEPTION(4, unknown_exception_entry
); /* Overflow */
105 DECLARE_EXCEPTION(5, unknown_exception_entry
); /* Bounds */
106 DECLARE_EXCEPTION(6, invalid_instruction_entry
); /* Invalid instruction */
107 DECLARE_EXCEPTION(7, unknown_exception_entry
); /* Device not present */
108 DECLARE_EXCEPTION(8, double_fault_entry
); /* Double fault */
109 DECLARE_EXCEPTION(9, unknown_exception_entry
); /* Co-processor segment overrun */
110 DECLARE_EXCEPTION(10, invalid_tss_exception_entry
);/* Invalid TSS */
111 DECLARE_EXCEPTION(11, seg_fault_entry
); /* Segment not present */
112 DECLARE_EXCEPTION(12, stack_fault_entry
); /* Stack overflow */
113 DECLARE_EXCEPTION(13, gpf_entry
); /* GPF */
114 DECLARE_EXCEPTION(14, page_fault_entry
); /* PF */
115 DECLARE_EXCEPTION(15, unknown_exception_entry
); /* Reserved */
116 DECLARE_EXCEPTION(16, fp_exception_entry
); /* Floating point */
117 DECLARE_EXCEPTION(17, alignment_check_entry
); /* alignment check */
118 DECLARE_EXCEPTION(18, machine_check_entry
); /* machine check */
119 DECLARE_EXCEPTION(19, unknown_exception_entry
); /* Reserved */
120 DECLARE_EXCEPTION(20, unknown_exception_entry
); /* Reserved */
121 DECLARE_EXCEPTION(21, unknown_exception_entry
); /* Reserved */
122 DECLARE_EXCEPTION(22, unknown_exception_entry
); /* Reserved */
123 DECLARE_EXCEPTION(23, unknown_exception_entry
); /* Reserved */
124 DECLARE_EXCEPTION(24, unknown_exception_entry
); /* Reserved */
125 DECLARE_EXCEPTION(25, unknown_exception_entry
); /* Reserved */
126 DECLARE_EXCEPTION(26, unknown_exception_entry
); /* Reserved */
127 DECLARE_EXCEPTION(27, unknown_exception_entry
); /* Reserved */
128 DECLARE_EXCEPTION(28, unknown_exception_entry
); /* Reserved */
129 DECLARE_EXCEPTION(29, unknown_exception_entry
); /* Reserved */
130 DECLARE_EXCEPTION(30, unknown_exception_entry
); /* Reserved */
131 DECLARE_EXCEPTION(31, unknown_exception_entry
); /* Reserved */
133 DECLARE_INTERRUPT(0);
134 DECLARE_INTERRUPT(1);
135 DECLARE_INTERRUPT(3);
136 DECLARE_INTERRUPT(4);
137 DECLARE_INTERRUPT(5);
138 DECLARE_INTERRUPT(6);
139 DECLARE_INTERRUPT(7);
140 DECLARE_INTERRUPT(8);
141 DECLARE_INTERRUPT(9);
142 DECLARE_INTERRUPT(10);
143 DECLARE_INTERRUPT(11);
144 DECLARE_INTERRUPT(12);
145 DECLARE_INTERRUPT(13);
146 DECLARE_INTERRUPT(14);
147 DECLARE_INTERRUPT(15);
149 void __attribute__ ((regparm(0))) default_isr(void);
150 asm ("default_isr: iret\n");
152 void disable_irq(int irq
)
154 if (irq
>= MAX_IRQ
) {
157 irq_table
[irq
].status
|= IRQ_DISABLED
;
161 void enable_irq(int irq
)
163 if (irq
>= MAX_IRQ
) {
166 irq_table
[irq
].status
&= ~IRQ_DISABLED
;
169 /* masks one specific IRQ in the PIC */
170 static void unmask_irq(int irq
)
174 if (irq
>= MAX_IRQ
) {
178 imr_port
= SLAVE_PIC
+ IMR
;
180 imr_port
= MASTER_PIC
+ IMR
;
183 outb(inb(imr_port
)&~(1<<(irq
&7)), imr_port
);
187 /* unmasks one specific IRQ in the PIC */
188 static void mask_irq(int irq
)
192 if (irq
>= MAX_IRQ
) {
196 imr_port
= SLAVE_PIC
+ IMR
;
198 imr_port
= MASTER_PIC
+ IMR
;
201 outb(inb(imr_port
)|(1<<(irq
&7)), imr_port
);
205 /* issue a Specific End Of Interrupt instruciton */
206 static void specific_eoi(int irq
)
208 /* If it is on the slave PIC this have to be performed on
209 * both the master and the slave PICs */
211 outb(OCW2_SEOI
|(irq
&7), SLAVE_PIC
+ OCW2
);
212 irq
= SEOI_IR2
; /* also do IR2 on master */
214 outb(OCW2_SEOI
|irq
, MASTER_PIC
+ OCW2
);
217 void __attribute__ ((regparm(0))) do_irq(int irq
)
222 if (irq_table
[irq
].status
& IRQ_DISABLED
) {
229 if (NULL
!= irq_table
[irq
].handler
) {
230 irq_handler_t
*handler
;
231 for (handler
= irq_table
[irq
].handler
;
232 NULL
!= handler
; handler
= handler
->next
) {
233 handler
->isr_func(handler
->isr_data
);
236 if ((irq
& 7) != 7) {
237 printf("Spurious irq %d\n", irq
);
245 void __attribute__ ((regparm(0))) unknown_exception_entry(int cause
, int ip
, int seg
)
247 printf("Unknown Exception %d at %04x:%08x\n", cause
, seg
, ip
);
250 void __attribute__ ((regparm(0))) divide_exception_entry(int cause
, int ip
, int seg
)
252 printf("Divide Error (Division by zero) at %04x:%08x\n", seg
, ip
);
256 void __attribute__ ((regparm(0))) debug_exception_entry(int cause
, int ip
, int seg
)
258 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg
, ip
);
261 void __attribute__ ((regparm(0))) nmi_entry(int cause
, int ip
, int seg
)
263 printf("NMI Interrupt at %04x:%08x\n", seg
, ip
);
266 void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause
, int ip
, int seg
)
268 printf("Invalid Instruction at %04x:%08x\n", seg
, ip
);
272 void __attribute__ ((regparm(0))) double_fault_entry(int cause
, int ip
, int seg
)
274 printf("Double fault at %04x:%08x\n", seg
, ip
);
278 void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause
, int ip
, int seg
)
280 printf("Invalid TSS at %04x:%08x\n", seg
, ip
);
283 void __attribute__ ((regparm(0))) seg_fault_entry(int cause
, int ip
, int seg
)
285 printf("Segmentation fault at %04x:%08x\n", seg
, ip
);
289 void __attribute__ ((regparm(0))) stack_fault_entry(int cause
, int ip
, int seg
)
291 printf("Stack fault at %04x:%08x\n", seg
, ip
);
295 void __attribute__ ((regparm(0))) gpf_entry(int cause
, int ip
, int seg
)
297 printf("General protection fault at %04x:%08x\n", seg
, ip
);
300 void __attribute__ ((regparm(0))) page_fault_entry(int cause
, int ip
, int seg
)
302 printf("Page fault at %04x:%08x\n", seg
, ip
);
306 void __attribute__ ((regparm(0))) fp_exception_entry(int cause
, int ip
, int seg
)
308 printf("Floating point exception at %04x:%08x\n", seg
, ip
);
311 void __attribute__ ((regparm(0))) alignment_check_entry(int cause
, int ip
, int seg
)
313 printf("Alignment check at %04x:%08x\n", seg
, ip
);
316 void __attribute__ ((regparm(0))) machine_check_entry(int cause
, int ip
, int seg
)
318 printf("Machine check exception at %04x:%08x\n", seg
, ip
);
322 void irq_install_handler(int ino
, interrupt_handler_t
*func
, void *pdata
)
330 if (NULL
!= irq_table
[ino
].handler
) {
334 status
= disable_interrupts();
335 irq_table
[ino
].handler
= malloc(sizeof(irq_handler_t
));
336 if (NULL
== irq_table
[ino
].handler
) {
340 memset(irq_table
[ino
].handler
, 0, sizeof(irq_handler_t
));
342 irq_table
[ino
].handler
->isr_func
= func
;
343 irq_table
[ino
].handler
->isr_data
= pdata
;
353 void irq_free_handler(int ino
)
360 status
= disable_interrupts();
362 if (NULL
== irq_table
[ino
].handler
) {
365 free(irq_table
[ino
].handler
);
366 irq_table
[ino
].handler
=NULL
;
375 ".word 0x800\n" /* size of the table 8*256 bytes */
376 ".long idt\n" /* offset */
377 ".word 0x18\n");/* data segment */
379 static void set_vector(int intnum
, void *routine
)
381 idt
[intnum
].base_high
= (u16
)((u32
)(routine
)>>16);
382 idt
[intnum
].base_low
= (u16
)((u32
)(routine
)&0xffff);
386 int interrupt_init(void)
390 /* Just in case... */
391 disable_interrupts();
393 /* Initialize the IDT and stuff */
396 memset(irq_table
, 0, sizeof(irq_table
));
399 for (i
=0;i
<256;i
++) {
400 idt
[i
].access
= 0x8e;
402 idt
[i
].selector
= 0x10;
403 set_vector(i
, default_isr
);
406 asm ("cs lidt idt_ptr\n");
408 /* Setup exceptions */
409 set_vector(0x00, exp_0
);
410 set_vector(0x01, exp_1
);
411 set_vector(0x02, exp_2
);
412 set_vector(0x03, exp_3
);
413 set_vector(0x04, exp_4
);
414 set_vector(0x05, exp_5
);
415 set_vector(0x06, exp_6
);
416 set_vector(0x07, exp_7
);
417 set_vector(0x08, exp_8
);
418 set_vector(0x09, exp_9
);
419 set_vector(0x0a, exp_10
);
420 set_vector(0x0b, exp_11
);
421 set_vector(0x0c, exp_12
);
422 set_vector(0x0d, exp_13
);
423 set_vector(0x0e, exp_14
);
424 set_vector(0x0f, exp_15
);
425 set_vector(0x10, exp_16
);
426 set_vector(0x11, exp_17
);
427 set_vector(0x12, exp_18
);
428 set_vector(0x13, exp_19
);
429 set_vector(0x14, exp_20
);
430 set_vector(0x15, exp_21
);
431 set_vector(0x16, exp_22
);
432 set_vector(0x17, exp_23
);
433 set_vector(0x18, exp_24
);
434 set_vector(0x19, exp_25
);
435 set_vector(0x1a, exp_26
);
436 set_vector(0x1b, exp_27
);
437 set_vector(0x1c, exp_28
);
438 set_vector(0x1d, exp_29
);
439 set_vector(0x1e, exp_30
);
440 set_vector(0x1f, exp_31
);
443 /* Setup interrupts */
444 set_vector(0x20, irq_0
);
445 set_vector(0x21, irq_1
);
446 set_vector(0x23, irq_3
);
447 set_vector(0x24, irq_4
);
448 set_vector(0x25, irq_5
);
449 set_vector(0x26, irq_6
);
450 set_vector(0x27, irq_7
);
451 set_vector(0x28, irq_8
);
452 set_vector(0x29, irq_9
);
453 set_vector(0x2a, irq_10
);
454 set_vector(0x2b, irq_11
);
455 set_vector(0x2c, irq_12
);
456 set_vector(0x2d, irq_13
);
457 set_vector(0x2e, irq_14
);
458 set_vector(0x2f, irq_15
);
459 /* vectors 0x30-0x3f are reserved for irq 16-31 */
462 /* Mask all interrupts */
463 outb(0xff, MASTER_PIC
+ IMR
);
464 outb(0xff, SLAVE_PIC
+ IMR
);
467 outb(ICW1_SEL
|ICW1_EICW4
, MASTER_PIC
+ ICW1
);
468 outb(0x20, MASTER_PIC
+ ICW2
); /* Place master PIC interrupts at INT20 */
469 outb(IR2
, MASTER_PIC
+ ICW3
); /* ICW3, One slevc PIC is present */
470 outb(ICW4_PM
, MASTER_PIC
+ ICW4
);
473 outb(OCW2_SEOI
|i
, MASTER_PIC
+ OCW2
);
477 outb(ICW1_SEL
|ICW1_EICW4
, SLAVE_PIC
+ ICW1
);
478 outb(0x28, SLAVE_PIC
+ ICW2
); /* Place slave PIC interrupts at INT28 */
479 outb(0x02, SLAVE_PIC
+ ICW3
); /* Slave ID */
480 outb(ICW4_PM
, SLAVE_PIC
+ ICW4
);
483 outb(OCW2_SEOI
|i
, SLAVE_PIC
+ OCW2
);
487 /* enable cascade interrerupt */
488 outb(0xfb, MASTER_PIC
+ IMR
);
489 outb(0xff, SLAVE_PIC
+ IMR
);
491 /* It is now safe to enable interrupts */
497 void enable_interrupts(void)
502 int disable_interrupts(void)
506 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags
) : );
508 return (flags
&0x200); /* IE flags is bit 9 */
512 #ifdef CONFIG_SYS_RESET_GENERIC
514 void __attribute__ ((regparm(0))) generate_gpf(void);
515 asm(".globl generate_gpf\n"
517 "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
519 void reset_cpu(ulong addr
)
521 set_vector(13, generate_gpf
); /* general protection fault handler */
522 set_vector(8, generate_gpf
); /* double fault handler */
523 generate_gpf(); /* start the show */