3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* stuff specific for the sc520,
25 * but idependent of implementation */
34 #ifdef CONFIG_SC520_SSI
39 #include <asm/ic/sc520.h>
41 DECLARE_GLOBAL_DATA_PTR
;
44 * utility functions for boards based on the AMD sc520
46 * void write_mmcr_byte(u16 mmcr, u8 data)
47 * void write_mmcr_word(u16 mmcr, u16 data)
48 * void write_mmcr_long(u16 mmcr, u32 data)
50 * u8 read_mmcr_byte(u16 mmcr)
51 * u16 read_mmcr_word(u16 mmcr)
52 * u32 read_mmcr_long(u16 mmcr)
54 * void init_sc520(void)
55 * unsigned long init_sc520_dram(void)
56 * void pci_sc520_init(struct pci_controller *hose)
58 * void reset_timer(void)
59 * ulong get_timer(ulong base)
60 * void set_timer(ulong t)
61 * void udelay(unsigned long usec)
65 static u32 mmcr_base
= 0xfffef000;
67 void write_mmcr_byte(u16 mmcr
, u8 data
)
69 writeb(data
, mmcr
+mmcr_base
);
72 void write_mmcr_word(u16 mmcr
, u16 data
)
74 writew(data
, mmcr
+mmcr_base
);
77 void write_mmcr_long(u16 mmcr
, u32 data
)
79 writel(data
, mmcr
+mmcr_base
);
82 u8
read_mmcr_byte(u16 mmcr
)
84 return readb(mmcr
+mmcr_base
);
87 u16
read_mmcr_word(u16 mmcr
)
89 return readw(mmcr
+mmcr_base
);
92 u32
read_mmcr_long(u16 mmcr
)
94 return readl(mmcr
+mmcr_base
);
100 /* Set the UARTxCTL register at it's slower,
101 * baud clock giving us a 1.8432 MHz reference
103 write_mmcr_byte(SC520_UART1CTL
, 7);
104 write_mmcr_byte(SC520_UART2CTL
, 7);
106 /* first set the timer pin mapping */
107 write_mmcr_byte(SC520_CLKSEL
, 0x72); /* no clock frequency selected, use 1.1892MHz */
109 /* enable PCI bus arbitrer */
110 write_mmcr_byte(SC520_SYSARBCTL
,0x02); /* enable concurrent mode */
112 write_mmcr_word(SC520_SYSARBMENB
,0x1f); /* enable external grants */
113 write_mmcr_word(SC520_HBCTL
,0x04); /* enable posted-writes */
116 if (CONFIG_SYS_SC520_HIGH_SPEED
) {
117 write_mmcr_byte(SC520_CPUCTL
, 0x2); /* set it to 133 MHz and write back */
118 gd
->cpu_clk
= 133000000;
119 printf("## CPU Speed set to 133MHz\n");
121 write_mmcr_byte(SC520_CPUCTL
, 1); /* set CPU to 100 MHz and write back cache */
122 printf("## CPU Speed set to 100MHz\n");
123 gd
->cpu_clk
= 100000000;
127 /* wait at least one millisecond */
128 asm("movl $0x2000,%%ecx\n"
129 "wait_loop: pushl %%ecx\n"
131 "loop wait_loop\n": : : "ecx");
133 /* turn on the SDRAM write buffer */
134 write_mmcr_byte(SC520_DBCTL
, 0x11);
136 /* turn on the cache and disable write through */
137 asm("movl %%cr0, %%eax\n"
138 "andl $0x9fffffff, %%eax\n"
139 "movl %%eax, %%cr0\n" : : : "eax");
142 unsigned long init_sc520_dram(void)
148 #ifdef CONFIG_SYS_SDRAM_DRCTMCTL
149 /* these memory control registers are set up in the assember part,
150 * in sc520_asm.S, during 'mem_init'. If we muck with them here,
151 * after we are running a stack in RAM, we have troubles. Besides,
152 * these refresh and delay values are better ? simply specified
153 * outright in the include/configs/{cfg} file since the HW designer
154 * simply dictates it.
159 int cas_precharge_delay
= CONFIG_SYS_SDRAM_PRECHARGE_DELAY
;
160 int refresh_rate
= CONFIG_SYS_SDRAM_REFRESH_RATE
;
161 int ras_cas_delay
= CONFIG_SYS_SDRAM_RAS_CAS_DELAY
;
163 /* set SDRAM speed here */
166 if (refresh_rate
<=1) {
168 } else if (refresh_rate
==2) {
169 val
= 1; /* 15.6us */
170 } else if (refresh_rate
==3 || refresh_rate
==4) {
171 val
= 2; /* 31.2us */
173 val
= 3; /* 62.4us */
176 write_mmcr_byte(SC520_DRCCTL
, (read_mmcr_byte(SC520_DRCCTL
) & 0xcf) | (val
<<4));
178 val
= read_mmcr_byte(SC520_DRCTMCTL
);
181 if (cas_precharge_delay
==3) {
182 val
|= 0x04; /* 3T */
183 } else if (cas_precharge_delay
==4) {
184 val
|= 0x08; /* 4T */
185 } else if (cas_precharge_delay
>4) {
189 if (ras_cas_delay
> 3) {
194 write_mmcr_byte(SC520_DRCTMCTL
, val
);
197 /* We read-back the configuration of the dram
198 * controller that the assembly code wrote */
199 dram_ctrl
= read_mmcr_long(SC520_DRCBENDADR
);
201 bd
->bi_dram
[0].start
= 0;
202 if (dram_ctrl
& 0x80) {
204 dram_present
= bd
->bi_dram
[1].start
= (dram_ctrl
& 0x7f) << 22;
205 bd
->bi_dram
[0].size
= bd
->bi_dram
[1].start
;
208 bd
->bi_dram
[0].size
= 0;
209 bd
->bi_dram
[1].start
= bd
->bi_dram
[0].start
;
212 if (dram_ctrl
& 0x8000) {
214 dram_present
= bd
->bi_dram
[2].start
= (dram_ctrl
& 0x7f00) << 14;
215 bd
->bi_dram
[1].size
= bd
->bi_dram
[2].start
- bd
->bi_dram
[1].start
;
217 bd
->bi_dram
[1].size
= 0;
218 bd
->bi_dram
[2].start
= bd
->bi_dram
[1].start
;
221 if (dram_ctrl
& 0x800000) {
223 dram_present
= bd
->bi_dram
[3].start
= (dram_ctrl
& 0x7f0000) << 6;
224 bd
->bi_dram
[2].size
= bd
->bi_dram
[3].start
- bd
->bi_dram
[2].start
;
226 bd
->bi_dram
[2].size
= 0;
227 bd
->bi_dram
[3].start
= bd
->bi_dram
[2].start
;
230 if (dram_ctrl
& 0x80000000) {
232 dram_present
= (dram_ctrl
& 0x7f000000) >> 2;
233 bd
->bi_dram
[3].size
= dram_present
- bd
->bi_dram
[3].start
;
235 bd
->bi_dram
[3].size
= 0;
240 printf("Configured %d bytes of dram\n", dram_present
);
242 gd
->ram_size
= dram_present
;
256 { SC520_IRQ0
, SC520_MPICMODE
, 0x01 },
257 { SC520_IRQ1
, SC520_MPICMODE
, 0x02 },
258 { SC520_IRQ2
, SC520_SL1PICMODE
, 0x02 },
259 { SC520_IRQ3
, SC520_MPICMODE
, 0x08 },
260 { SC520_IRQ4
, SC520_MPICMODE
, 0x10 },
261 { SC520_IRQ5
, SC520_MPICMODE
, 0x20 },
262 { SC520_IRQ6
, SC520_MPICMODE
, 0x40 },
263 { SC520_IRQ7
, SC520_MPICMODE
, 0x80 },
265 { SC520_IRQ8
, SC520_SL1PICMODE
, 0x01 },
266 { SC520_IRQ9
, SC520_SL1PICMODE
, 0x02 },
267 { SC520_IRQ10
, SC520_SL1PICMODE
, 0x04 },
268 { SC520_IRQ11
, SC520_SL1PICMODE
, 0x08 },
269 { SC520_IRQ12
, SC520_SL1PICMODE
, 0x10 },
270 { SC520_IRQ13
, SC520_SL1PICMODE
, 0x20 },
271 { SC520_IRQ14
, SC520_SL1PICMODE
, 0x40 },
272 { SC520_IRQ15
, SC520_SL1PICMODE
, 0x80 }
276 /* The interrupt used for PCI INTA-INTD */
277 int sc520_pci_ints
[15] = {
278 -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1
282 /* utility function to configure a pci interrupt */
283 int pci_sc520_set_irq(int pci_pin
, int irq
)
288 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin
+ 'A', irq
);
290 if (irq
< 0 || irq
> 15) {
291 return -1; /* illegal irq */
294 if (pci_pin
< 0 || pci_pin
> 15) {
295 return -1; /* illegal pci int pin */
298 /* first disable any non-pci interrupt source that use
300 for (i
=SC520_GPTMR0MAP
;i
<=SC520_GP10IMAP
;i
++) {
301 if (i
>=SC520_PCIINTAMAP
&&i
<=SC520_PCIINTDMAP
) {
304 if (read_mmcr_byte(i
) == sc520_irq
[irq
].priority
) {
305 write_mmcr_byte(i
, SC520_IRQ_DISABLED
);
309 /* Set the trigger to level */
310 write_mmcr_byte(sc520_irq
[irq
].level_reg
,
311 read_mmcr_byte(sc520_irq
[irq
].level_reg
) | sc520_irq
[irq
].level_bit
);
316 /* route the interrupt */
317 write_mmcr_byte(SC520_PCIINTAMAP
+ pci_pin
, sc520_irq
[irq
].priority
);
321 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
322 write_mmcr_byte(SC520_GP0IMAP
+ pci_pin
- 4, sc520_irq
[irq
].priority
);
324 /* also set the polarity in this case */
325 write_mmcr_word(SC520_INTPINPOL
,
326 read_mmcr_word(SC520_INTPINPOL
) | (1 << (pci_pin
-4)));
330 /* register the pin */
331 sc520_pci_ints
[pci_pin
] = irq
;
337 void pci_sc520_init(struct pci_controller
*hose
)
339 hose
->first_busno
= 0;
340 hose
->last_busno
= 0xff;
342 /* System memory space */
343 pci_set_region(hose
->regions
+ 0,
344 SC520_PCI_MEMORY_BUS
,
345 SC520_PCI_MEMORY_PHYS
,
346 SC520_PCI_MEMORY_SIZE
,
347 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
349 /* PCI memory space */
350 pci_set_region(hose
->regions
+ 1,
356 /* ISA/PCI memory space */
357 pci_set_region(hose
->regions
+ 2,
364 pci_set_region(hose
->regions
+ 3,
370 /* ISA/PCI I/O space */
371 pci_set_region(hose
->regions
+ 4,
377 hose
->region_count
= 5;
379 pci_setup_type1(hose
,
383 pci_register_hose(hose
);
385 hose
->last_busno
= pci_hose_scan(hose
);
387 /* enable target memory acceses on host brige */
388 pci_write_config_word(0, PCI_COMMAND
,
389 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
396 #ifdef CONFIG_SYS_TIMER_SC520
399 void reset_timer(void)
401 write_mmcr_word(SC520_GPTMR0CNT
, 0);
402 write_mmcr_word(SC520_GPTMR0CTL
, 0x6001);
406 ulong
get_timer(ulong base
)
408 /* fixme: 30 or 33 */
409 return read_mmcr_word(SC520_GPTMR0CNT
) / 33;
412 void set_timer(ulong t
)
414 /* FixMe: use two cascade coupled timers */
415 write_mmcr_word(SC520_GPTMR0CTL
, 0x4001);
416 write_mmcr_word(SC520_GPTMR0CNT
, t
*33);
417 write_mmcr_word(SC520_GPTMR0CTL
, 0x6001);
421 void udelay(unsigned long usec
)
426 read_mmcr_word(SC520_SWTMRMILLI
);
427 read_mmcr_word(SC520_SWTMRMICRO
);
430 /* do not enable this line, udelay is used in the serial driver -> recursion */
431 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec
, m
, u
, tm
, tu
);
435 m
+= read_mmcr_word(SC520_SWTMRMILLI
);
436 u
= read_mmcr_word(SC520_SWTMRMICRO
) + (m
* 1000);
446 int ssi_set_interface(int freq
, int lsb_first
, int inv_clock
, int inv_phase
)
451 temp
|= CTL_CLK_SEL_4
;
452 } else if (freq
>= 4096) {
453 temp
|= CTL_CLK_SEL_8
;
454 } else if (freq
>= 2048) {
455 temp
|= CTL_CLK_SEL_16
;
456 } else if (freq
>= 1024) {
457 temp
|= CTL_CLK_SEL_32
;
458 } else if (freq
>= 512) {
459 temp
|= CTL_CLK_SEL_64
;
460 } else if (freq
>= 256) {
461 temp
|= CTL_CLK_SEL_128
;
462 } else if (freq
>= 128) {
463 temp
|= CTL_CLK_SEL_256
;
465 temp
|= CTL_CLK_SEL_512
;
480 write_mmcr_byte(SC520_SSICTL
, temp
);
485 u8
ssi_txrx_byte(u8 data
)
487 write_mmcr_byte(SC520_SSIXMIT
, data
);
488 while ((read_mmcr_byte(SC520_SSISTA
)) & SSISTA_BSY
);
489 write_mmcr_byte(SC520_SSICMD
, SSICMD_CMD_SEL_XMITRCV
);
490 while ((read_mmcr_byte(SC520_SSISTA
)) & SSISTA_BSY
);
491 return read_mmcr_byte(SC520_SSIRCV
);
495 void ssi_tx_byte(u8 data
)
497 write_mmcr_byte(SC520_SSIXMIT
, data
);
498 while ((read_mmcr_byte(SC520_SSISTA
)) & SSISTA_BSY
);
499 write_mmcr_byte(SC520_SSICMD
, SSICMD_CMD_SEL_XMIT
);
504 while ((read_mmcr_byte(SC520_SSISTA
)) & SSISTA_BSY
);
505 write_mmcr_byte(SC520_SSICMD
, SSICMD_CMD_SEL_RCV
);
506 while ((read_mmcr_byte(SC520_SSISTA
)) & SSISTA_BSY
);
507 return read_mmcr_byte(SC520_SSIRCV
);
510 #endif /* CONFIG_SC520 */