cpu/i386/sc520_asm.S

   1 /*
   2  * (C) Copyright 2002
   3  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* This file is largely based on code obtned from AMD. AMD's original
  25  * copyright is included below
  26  */
  27
  28 /*
  29  *  =============================================================================
  30  *
  31  *   Copyright 1999 Advanced Micro Devices, Inc.
  32  *
  33  *  This software is the property of Advanced Micro Devices, Inc  (AMD)  which
  34  *  specifically grants the user the right to modify, use and distribute this
  35  *  software provided this COPYRIGHT NOTICE is not removed or altered.  All
  36  *  other rights are reserved by AMD.
  37  *
  38  *  THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
  39  *  OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
  40  *  THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
  41  *  IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
  42  *  (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
  43  *  INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
  44  *  TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
  45  *  SUCH DAMAGES.  BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
  46  *  LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
  47  *  LIMITATION MAY NOT APPLY TO YOU.
  48  *
  49  *  AMD does not assume any responsibility for any errors that may appear in
  50  *  the Materials nor any responsibility to support or update the Materials.
  51  *  AMD retains the right to make changes to its test specifications at any
  52  *  time, without notice.
  53  *
  54  *  So that all may benefit from your experience, please report  any  problems
  55  *  or suggestions about this software back to AMD.  Please include your name,
  56  *  company,  telephone number,  AMD product requiring support and question or
  57  *  problem encountered.
  58  *
  59  *  Advanced Micro Devices, Inc.         Worldwide support and contact
  60  *  Embedded Processor Division            information available at:
  61  *  Systems Engineering                       epd.support@amd.com
  62  *  5204 E. Ben White Blvd.                          -or-
  63  *  Austin, TX 78741                http://www.amd.com/html/support/techsup.html
  64  *  ============================================================================
  65  */
  66
  67
  68 /*******************************************************************************
  69  *       AUTHOR      : Buddy Fey - Original.
  70  *******************************************************************************
  71  */
  72
  73
  74 /*******************************************************************************
  75  *       FUNCTIONAL DESCRIPTION:
  76  * This routine is called to autodetect the geometry of the DRAM.
  77  *
  78  * This routine is called to determine the number of column bits for the DRAM
  79  * devices in this external bank. This routine assumes that the external bank
  80  * has been configured for an 11-bit column and for 4 internal banks. This gives
  81  * us the maximum address reach in memory. By writing a test value to the max
  82  * address and locating where it aliases to, we can determine the number of valid
  83  * column bits.
  84  *
  85  * This routine is called to determine the number of internal banks each DRAM
  86  * device has. The external bank (under test) is configured for maximum reach
  87  * with 11-bit columns and 4 internal banks. This routine will write to a max
  88  * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
  89  * that column is a "don't care". If BA1 does not affect write/read of data,
  90  * then this device has only 2 internal banks.
  91  *
  92  * This routine is called to determine the ending address for this external
  93  * bank of SDRAM. We write to a max address with a data value and then disable
  94  * row address bits looking for "don't care" locations. Each "don't care" bit
  95  * represents a dividing of the maximum density (128M) by 2. By dividing the
  96  * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
  97  * determined during sizing, we set the proper density.
  98  *
  99  * WARNINGS.
 100  * bp must be preserved because it is used for return linkage.
 101  *
 102  * EXIT
 103  * nothing returned - but the memory subsystem is enabled
 104  *******************************************************************************
 105  */
 106
 107 #include <config.h>
 108 #ifdef CONFIG_SC520
 109
 110 .section .text
 111 .equ            DRCCTL,     0x0fffef010   /* DRAM control register */
 112 .equ            DRCTMCTL,   0x0fffef012   /* DRAM timing control register */
 113 .equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
 114 .equ            DRCBENDADR, 0x0fffef018   /* DRAM bank ending address register */
 115 .equ            ECCCTL,     0x0fffef020   /* DRAM ECC control register */
 116 .equ            ECCINT,     0x0fffefd18   /* DRAM ECC nmi-INT mapping */
 117 .equ            DBCTL,      0x0fffef040   /* DRAM buffer control register */
 118
 119 .equ            CACHELINESZ, 0x00000010   /* size of our cache line (read buffer) */
 120 .equ            COL11_ADR,  0x0e001e00    /* 11 col addrs */
 121 .equ            COL10_ADR,  0x0e000e00    /* 10 col addrs */
 122 .equ            COL09_ADR,  0x0e000600    /*  9 col addrs */
 123 .equ            COL08_ADR,  0x0e000200    /*  8 col addrs */
 124 .equ            ROW14_ADR,  0x0f000000    /* 14 row addrs */
 125 .equ            ROW13_ADR,  0x07000000    /* 13 row addrs */
 126 .equ            ROW12_ADR,  0x03000000    /* 12 row addrs */
 127 .equ            ROW11_ADR,  0x01000000    /* 11 row addrs/also bank switch */
 128 .equ            ROW10_ADR,  0x00000000    /* 10 row addrs/also bank switch */
 129 .equ            COL11_DATA, 0x0b0b0b0b    /* 11 col addrs */
 130 .equ            COL10_DATA, 0x0a0a0a0a    /* 10 col data */
 131 .equ            COL09_DATA, 0x09090909    /*  9 col data */
 132 .equ            COL08_DATA, 0x08080808    /*  8 col data */
 133 .equ            ROW14_DATA, 0x3f3f3f3f    /* 14 row data (MASK) */
 134 .equ            ROW13_DATA, 0x1f1f1f1f    /* 13 row data (MASK) */
 135 .equ            ROW12_DATA, 0x0f0f0f0f    /* 12 row data (MASK) */
 136 .equ            ROW11_DATA, 0x07070707    /* 11 row data/also bank switch (MASK) */
 137 .equ            ROW10_DATA, 0xaaaaaaaa    /* 10 row data/also bank switch (MASK) */
 138
 139
 140  /*
 141   * initialize dram controller registers
 142   */
 143 .globl mem_init
 144 mem_init:
 145         xorw    %ax,%ax
 146         movl    $DBCTL, %edi
 147         movb     %al, (%edi)             /* disable write buffer */
 148
 149         movl    $ECCCTL, %edi
 150         movb     %al, (%edi)             /* disable ECC */
 151
 152         movl    $DRCTMCTL, %edi
 153         movb    $0x1E,%al                /* Set SDRAM timing for slowest */
 154         movb     %al, (%edi)
 155
 156  /*
 157   * setup loop to do 4 external banks starting with bank 3
 158   */
 159         movl    $0xff000000,%eax         /* enable last bank and setup */
 160         movl    $DRCBENDADR, %edi        /* ending address register */
 161         movl     %eax, (%edi)
 162
 163         movl    $DRCCFG, %edi            /* setup */
 164         movw    $0xbbbb,%ax              /* dram config register for  */
 165         movw    %ax, (%edi)
 166
 167  /*
 168   * issue a NOP to all DRAMs
 169   */
 170         movl    $DRCCTL, %edi            /* setup DRAM control register with */
 171         movb    $0x1,%al                 /* Disable refresh,disable write buffer */
 172         movb     %al, (%edi)
 173         movl    $CACHELINESZ, %esi       /* just a dummy address to write for */
 174         movw     %ax, (%esi)
 175  /*
 176   * delay for 100 usec? 200?
 177   * ******this is a cludge for now *************
 178   */
 179         movw    $100,%cx
 180 sizdelay:
 181         loop    sizdelay                 /* we need 100 usec here */
 182  /***********************************************/
 183
 184  /*
 185   * issue all banks precharge
 186   */
 187         movb    $0x2,%al                 /* All banks precharge */
 188         movb     %al, (%edi)
 189         movw     %ax, (%esi)
 190
 191  /*
 192   * issue 2 auto refreshes to all banks
 193   */
 194         movb    $0x4,%al                 /* Auto refresh cmd */
 195         movb     %al, (%edi)
 196         movw    $2,%cx
 197 refresh1:
 198         movw     %ax, (%esi)
 199         loop    refresh1
 200
 201  /*
 202   * issue LOAD MODE REGISTER command
 203   */
 204         movb    $0x3,%al                 /* Load mode register cmd */
 205         movb     %al, (%edi)
 206         movw     %ax, (%esi)
 207
 208  /*
 209   * issue 8 more auto refreshes to all banks
 210   */
 211         movb    $0x4,%al                 /* Auto refresh cmd */
 212         movb     %al, (%edi)
 213         movw    $8,%cx
 214 refresh2:
 215         movw     %ax, (%esi)
 216         loop    refresh2
 217
 218  /*
 219   * set control register to NORMAL mode
 220   */
 221         movb    $0x0,%al                 /* Normal mode value */
 222         movb     %al, (%edi)
 223
 224  /*
 225   * size dram starting with external bank 3 moving to external bank 0
 226   */
 227         movl    $0x3,%ecx                /* start with external bank 3 */
 228
 229 nextbank:
 230
 231  /*
 232   * write col 11 wrap adr
 233   */
 234         movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
 235         movl    $COL11_DATA, %eax        /* pattern for max supported columns(11) */
 236         movl    %eax, (%esi)             /* write max col pattern at max col adr */
 237         movl    (%esi), %ebx             /* optional read */
 238         cmpl    %ebx,%eax                /* to verify write */
 239         jnz     bad_ram                  /* this ram is bad */
 240  /*
 241   * write col 10 wrap adr
 242   */
 243
 244         movl    $COL10_ADR, %esi         /* set address to 10 col wrap address */
 245         movl    $COL10_DATA, %eax        /* pattern for 10 col wrap */
 246         movl    %eax, (%esi)             /* write 10 col pattern @ 10 col wrap adr */
 247         movl    (%esi), %ebx             /* optional read */
 248         cmpl    %ebx,%eax                /* to verify write */
 249         jnz     bad_ram                  /* this ram is bad */
 250  /*
 251   * write col 9 wrap adr
 252   */
 253         movl    $COL09_ADR, %esi         /* set address to 9 col wrap address */
 254         movl    $COL09_DATA, %eax        /* pattern for 9 col wrap */
 255         movl    %eax, (%esi)             /* write 9 col pattern @ 9 col wrap adr */
 256         movl    (%esi), %ebx             /* optional read */
 257         cmpl    %ebx,%eax                /* to verify write */
 258         jnz     bad_ram                  /* this ram is bad */
 259  /*
 260   * write col 8 wrap adr
 261   */
 262         movl    $COL08_ADR, %esi         /* set address to min(8) col wrap address */
 263         movl    $COL08_DATA, %eax        /* pattern for min (8) col wrap */
 264         movl    %eax, (%esi)             /* write min col pattern @ min col adr */
 265         movl    (%esi), %ebx             /* optional read */
 266         cmpl    %ebx,%eax                /* to verify write */
 267         jnz     bad_ram                  /* this ram is bad */
 268  /*
 269   * write row 14 wrap adr
 270   */
 271         movl    $ROW14_ADR, %esi         /* set address to max row (14) wrap addr */
 272         movl    $ROW14_DATA, %eax        /* pattern for max supported rows(14) */
 273         movl    %eax, (%esi)             /* write max row pattern at max row adr */
 274         movl    (%esi), %ebx             /* optional read */
 275         cmpl    %ebx,%eax                /* to verify write */
 276         jnz     bad_ram                  /* this ram is bad */
 277  /*
 278   * write row 13 wrap adr
 279   */
 280         movl    $ROW13_ADR, %esi         /* set address to 13 row wrap address */
 281         movl    $ROW13_DATA, %eax        /* pattern for 13 row wrap */
 282         movl    %eax, (%esi)             /* write 13 row pattern @ 13 row wrap adr */
 283         movl    (%esi), %ebx             /* optional read */
 284         cmpl    %ebx,%eax                /* to verify write */
 285         jnz     bad_ram                  /* this ram is bad */
 286  /*
 287   * write row 12 wrap adr
 288   */
 289         movl    $ROW12_ADR, %esi         /* set address to 12 row wrap address */
 290         movl    $ROW12_DATA, %eax        /* pattern for 12 row wrap */
 291         movl    %eax, (%esi)             /* write 12 row pattern @ 12 row wrap adr */
 292         movl    (%esi), %ebx             /* optional read */
 293         cmpl    %ebx,%eax                /* to verify write */
 294         jnz     bad_ram                  /* this ram is bad */
 295  /*
 296   * write row 11 wrap adr
 297   */
 298         movl    $ROW11_ADR, %edi         /* set address to 11 row wrap address */
 299         movl    $ROW11_DATA, %eax        /* pattern for 11 row wrap */
 300         movl    %eax, (%edi)             /* write 11 row pattern @ 11 row wrap adr */
 301         movl    (%edi), %ebx             /* optional read */
 302         cmpl    %ebx,%eax                /* to verify write */
 303         jnz     bad_ram                  /* this ram is bad */
 304  /*
 305   * write row 10 wrap adr --- this write is really to determine number of banks
 306   */
 307         movl    $ROW10_ADR, %edi         /* set address to 10 row wrap address */
 308         movl    $ROW10_DATA, %eax        /* pattern for 10 row wrap (AA) */
 309         movl    %eax, (%edi)             /* write 10 row pattern @ 10 row wrap adr */
 310         movl    (%edi), %ebx             /* optional read */
 311         cmpl    %ebx,%eax                /* to verify write */
 312         jnz     bad_ram                  /* this ram is bad */
 313  /*
 314   * read data @ row 12 wrap adr to determine  * banks,
 315   * and read data @ row 14 wrap adr to determine  * rows.
 316   * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
 317   * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
 318   * if data @ row 12 wrap == 11 or 12, we have 4 banks,
 319   */
 320         xorw    %di,%di                  /* value for 2 banks in DI */
 321         movl    (%esi), %ebx             /* read from 12 row wrap to check banks
 322                                           * (esi is setup from the write to row 12 wrap) */
 323         cmpl    %ebx,%eax                /* check for AA pattern  (eax holds the aa pattern) */
 324         jz      only2                    /* if pattern == AA, we only have 2 banks */
 325
 326         /* 4 banks */
 327
 328         movw    $8,%di                   /* value for 4 banks in DI (BNK_CNT bit) */
 329         cmpl    $ROW11_DATA, %ebx        /* only other legitimate values are 11 */
 330         jz      only2
 331         cmpl    $ROW12_DATA, %ebx        /* and 12 */
 332         jnz     bad_ram                  /* its bad if not 11 or 12! */
 333
 334         /* fall through */
 335 only2:
 336  /*
 337   * validate row mask
 338   */
 339         movl    $ROW14_ADR, %esi         /* set address back to max row wrap addr */
 340         movl    (%esi), %eax             /* read actual number of rows @ row14 adr */
 341
 342         cmpl    $ROW11_DATA, %eax        /* row must be greater than 11 pattern */
 343         jb      bad_ram
 344
 345         cmpl    $ROW14_DATA, %eax        /* and row must be less than 14 pattern */
 346         ja      bad_ram
 347
 348         cmpb    %ah,%al                  /* verify all 4 bytes of dword same */
 349         jnz     bad_ram
 350         movl    %eax,%ebx
 351         shrl    $16,%ebx
 352         cmpw    %bx,%ax
 353         jnz     bad_ram
 354  /*
 355   * read col 11 wrap adr for real column data value
 356   */
 357         movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
 358         movl    (%esi), %eax             /* read real col number at max col adr */
 359  /*
 360   * validate column data
 361   */
 362         cmpl    $COL08_DATA, %eax        /* col must be greater than 8 pattern */
 363         jb      bad_ram
 364
 365         cmpl    $COL11_DATA, %eax        /* and row must be less than 11 pattern */
 366         ja      bad_ram
 367
 368         subl    $COL08_DATA, %eax        /* normalize column data to zero */
 369         jc      bad_ram
 370         cmpb    %ah,%al                  /* verify all 4 bytes of dword equal */
 371         jnz     bad_ram
 372         movl    %eax,%edx
 373         shrl    $16,%edx
 374         cmpw    %dx,%ax
 375         jnz     bad_ram
 376  /*
 377   * merge bank and col data together
 378   */
 379         addw    %di,%dx                  /* merge of bank and col info in dl */
 380  /*
 381   * fix ending addr mask based upon col info
 382   */
 383         movb    $3,%al
 384         subb    %dh,%al                  /* dh contains the overflow from the bank/col merge  */
 385         movb    %bl,%dh                  /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
 386         xchgw   %cx,%ax                  /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
 387         shrb    %cl,%dh                  /*  */
 388         incb    %dh                      /* ending addr is 1 greater than real end */
 389         xchgw   %cx,%ax                  /* cx is bank number again */
 390  /*
 391   * issue all banks precharge
 392   */
 393 bad_reint:
 394         movl    $DRCCTL, %esi            /* setup DRAM control register with */
 395         movb    $0x2,%al                 /* All banks precharge */
 396         movb     %al, (%esi)
 397         movl    $CACHELINESZ, %esi       /* address to init read buffer */
 398         movw     %ax, (%esi)
 399
 400  /*
 401   * update ENDING ADDRESS REGISTER
 402   */
 403         movl    $DRCBENDADR, %edi        /* DRAM ending address register */
 404         movl    %ecx,%ebx
 405         addl    %ebx, %edi
 406         movb    %dh, (%edi)
 407  /*
 408   * update CONFIG REGISTER
 409   */
 410         xorb    %dh,%dh
 411         movw    $0x00f,%bx
 412         movw    %cx,%ax
 413         shlw    $2,%ax
 414         xchgw   %cx,%ax
 415         shlw    %cl,%dx
 416         shlw    %cl,%bx
 417         notw    %bx
 418         xchgw   %cx,%ax
 419         movl    $DRCCFG, %edi
 420         mov     (%edi), %ax
 421         andw    %bx,%ax
 422         orw     %dx,%ax
 423         movw    %ax, (%edi)
 424         jcxz    cleanup
 425
 426         decw    %cx
 427         movl    %ecx,%ebx
 428         movl    $DRCBENDADR, %edi        /* DRAM ending address register */
 429         movb    $0xff,%al
 430         addl    %ebx, %edi
 431         movb    %al, (%edi)
 432  /*
 433   * set control register to NORMAL mode
 434   */
 435         movl    $DRCCTL, %esi            /* setup DRAM control register with */
 436         movb    $0x0,%al                 /* Normal mode value */
 437         movb    %al, (%esi)
 438         movl    $CACHELINESZ, %esi       /* address to init read buffer */
 439         movw    %ax, (%esi)
 440         jmp     nextbank
 441
 442 cleanup:
 443         movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
 444         movw    $4,%cx
 445         xorw    %ax,%ax
 446 cleanuplp:
 447         movb   (%edi), %al
 448         orb     %al,%al
 449         jz      emptybank
 450
 451         addb    %ah,%al
 452         jns     nottoomuch
 453
 454         movb    $0x7f,%al
 455 nottoomuch:
 456         movb    %al,%ah
 457         orb     $0x80,%al
 458         movb    %al, (%edi)
 459 emptybank:
 460         incl    %edi
 461         loop    cleanuplp
 462
 463 #if defined CONFIG_SYS_SDRAM_DRCTMCTL
 464         /* just have your hardware desinger _GIVE_ you what you need here! */
 465         movl    $DRCTMCTL, %edi
 466         movb    $CONFIG_SYS_SDRAM_DRCTMCTL,%al
 467         movb    (%edi), %al
 468 #else
 469 #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
 470         /* set the CAS latency now since it is hard to do
 471          * when we run from the RAM */
 472         movl    $DRCTMCTL, %edi          /* DRAM timing register */
 473         movb    (%edi), %al
 474 #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 475         andb    $0xef, %al
 476 #endif
 477 #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 478         orb     $0x10, %al
 479 #endif
 480         movb    %al, (%edi)
 481 #endif
 482 #endif
 483         movl    $DRCCTL, %edi            /* DRAM Control register */
 484         movb    $0x3,%al                 /* Load mode register cmd */
 485         movb     %al, (%edi)
 486         movw     %ax, (%esi)
 487
 488
 489         movl    $DRCCTL, %edi            /* DRAM Control register */
 490         movb    $0x18,%al                /*  Enable refresh and NORMAL mode */
 491         movb    %al, (%edi)
 492
 493         jmp     dram_done
 494
 495 bad_ram:
 496         xorl    %edx,%edx
 497         xorl    %edi,%edi
 498         jmp     bad_reint
 499
 500 dram_done:
 501
 502         /* readback DRCBENDADR and return the number
 503          * of available ram bytes in %eax */
 504
 505         movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
 506
 507         movl    (%edi), %eax
 508         movl    %eax, %ecx
 509         andl    $0x80000000, %ecx
 510         jz      bank2
 511         andl    $0x7f000000, %eax
 512         shrl    $2, %eax
 513         movl    %eax, %ebx
 514
 515 bank2:  movl    (%edi), %eax
 516         movl    %eax, %ecx
 517         andl    $0x00800000, %ecx
 518         jz      bank1
 519         andl    $0x007f0000, %eax
 520         shll    $6, %eax
 521         movl    %eax, %ebx
 522
 523 bank1:  movl    (%edi), %eax
 524         movl    %eax, %ecx
 525         andl    $0x00008000, %ecx
 526         jz      bank0
 527         andl    $0x00007f00, %eax
 528         shll    $14, %eax
 529         movl    %eax, %ebx
 530
 531 bank0:  movl    (%edi), %eax
 532         movl    %eax, %ecx
 533         andl    $0x00000080, %ecx
 534         jz      done
 535         andl    $0x0000007f, %eax
 536         shll    $22, %eax
 537         movl    %eax, %ebx
 538
 539
 540 done:
 541         movl    %ebx, %eax
 542
 543 #if CONFIG_SYS_SDRAM_ECC_ENABLE
 544         /* A nominal memory test: just a byte at each address line */
 545         movl    %eax, %ecx
 546         shrl    $0x1, %ecx
 547         movl    $0x1, %edi
 548 memtest0:
 549         movb    $0xa5, (%edi)
 550         cmpb    $0xa5, (%edi)
 551         jne     out
 552         shrl    $1, %ecx
 553         andl    %ecx,%ecx
 554         jz      set_ecc
 555         shll    $1, %edi
 556         jmp     memtest0
 557
 558 set_ecc:
 559         /* clear all ram with a memset */
 560         movl    %eax, %ecx
 561         xorl    %esi, %esi
 562         xorl    %edi, %edi
 563         xorl    %eax, %eax
 564         shrl    $2, %ecx
 565         cld
 566         rep     stosl
 567                         /* enable read, write buffers */
 568         movb    $0x11, %al
 569         movl    $DBCTL, %edi
 570         movb    %al, (%edi)
 571                         /* enable NMI mapping for ECC */
 572         movl    $ECCINT, %edi
 573         mov     $0x10, %al
 574         movb    %al, (%edi)
 575                         /* Turn on ECC */
 576         movl    $ECCCTL, %edi
 577         mov     $0x05, %al
 578         movb    %al, (%edi)
 579 #endif
 580 out:
 581         movl    %ebx, %eax
 582         jmp     *%ebp
 583
 584 #endif /* CONFIG_SC520 */