cpu/ixp/npe/include/IxAtmTypes.h

   1 /**
   2  * @file IxAtmTypes.h
   3  *
   4  * @date 24-MAR-2002
   5  *
   6  * @brief This file contains Atm types common to a number of Atm components.
   7  *
   8  * @par
   9  * IXP400 SW Release version 2.0
  10  *
  11  * -- Copyright Notice --
  12  *
  13  * @par
  14  * Copyright 2001-2005, Intel Corporation.
  15  * All rights reserved.
  16  *
  17  * @par
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions
  20  * are met:
  21  * 1. Redistributions of source code must retain the above copyright
  22  *    notice, this list of conditions and the following disclaimer.
  23  * 2. Redistributions in binary form must reproduce the above copyright
  24  *    notice, this list of conditions and the following disclaimer in the
  25  *    documentation and/or other materials provided with the distribution.
  26  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  27  *    may be used to endorse or promote products derived from this software
  28  *    without specific prior written permission.
  29  *
  30  * @par
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  32  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  33  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  34  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  35  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  39  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  40  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  41  * SUCH DAMAGE.
  42  *
  43  * @par
  44  * -- End of Copyright Notice --
  45  */
  46
  47 /* ------------------------------------------------------
  48    Doxygen group definitions
  49    ------------------------------------------------------ */
  50 /**
  51  * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
  52  *
  53  * @brief The common set of types used in many Atm components
  54  *
  55  * @{ */
  56
  57 #ifndef IXATMTYPES_H
  58 #define IXATMTYPES_H
  59
  60 #include "IxNpeA.h"
  61
  62 /**
  63  * @enum IxAtmLogicalPort
  64  *
  65  * @brief Logical Port Definitions  :
  66  *
  67  * Only 1 port is available in SPHY configuration
  68  * 12 ports are enabled in MPHY configuration
  69  *
  70  */
  71 typedef enum
  72 {
  73     IX_UTOPIA_PORT_0 = 0,  /**< Port 0 */
  74 #ifdef IX_NPE_MPHYMULTIPORT
  75     IX_UTOPIA_PORT_1,      /**< Port 1 */
  76     IX_UTOPIA_PORT_2,      /**< Port 2 */
  77     IX_UTOPIA_PORT_3,      /**< Port 3 */
  78     IX_UTOPIA_PORT_4,      /**< Port 4 */
  79     IX_UTOPIA_PORT_5,      /**< Port 5 */
  80     IX_UTOPIA_PORT_6,      /**< Port 6 */
  81     IX_UTOPIA_PORT_7,      /**< Port 7 */
  82     IX_UTOPIA_PORT_8,      /**< Port 8 */
  83     IX_UTOPIA_PORT_9,      /**< Port 9 */
  84     IX_UTOPIA_PORT_10,     /**< Port 10 */
  85     IX_UTOPIA_PORT_11,     /**< Port 11 */
  86 #endif /* IX_NPE_MPHY */
  87     IX_UTOPIA_MAX_PORTS    /**< Not a port - just a definition for the
  88                            * maximum possible ports
  89                            */
  90 } IxAtmLogicalPort;
  91
  92 /**
  93  * @def IX_ATM_CELL_PAYLOAD_SIZE
  94  * @brief Size of a ATM cell payload
  95  */
  96 #define IX_ATM_CELL_PAYLOAD_SIZE             (48)
  97
  98 /**
  99  * @def IX_ATM_CELL_SIZE
 100  * @brief Size of a ATM cell, including header
 101  */
 102 #define IX_ATM_CELL_SIZE                     (53)
 103
 104 /**
 105  * @def IX_ATM_CELL_SIZE_NO_HEC
 106  * @brief Size of a ATM cell, excluding HEC byte
 107  */
 108 #define IX_ATM_CELL_SIZE_NO_HEC              (IX_ATM_CELL_SIZE - 1)
 109
 110 /**
 111  * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
 112  * @brief Size of a OAM cell, excluding HEC byte
 113  */
 114 #define IX_ATM_OAM_CELL_SIZE_NO_HEC          IX_ATM_CELL_SIZE_NO_HEC
 115
 116 /**
 117  * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
 118  * @brief Size of a AAL0 48 Cell payload
 119  */
 120 #define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE     IX_ATM_CELL_PAYLOAD_SIZE
 121
 122 /**
 123  * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
 124  * @brief Size of a AAL5 Cell payload
 125  */
 126 #define IX_ATM_AAL5_CELL_PAYLOAD_SIZE        IX_ATM_CELL_PAYLOAD_SIZE
 127
 128 /**
 129  * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
 130  * @brief Size of a AAL0 52 Cell, excluding HEC byte
 131  */
 132 #define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC      IX_ATM_CELL_SIZE_NO_HEC
 133
 134
 135 /**
 136  * @def IX_ATM_MAX_VPI
 137  * @brief Maximum value of an ATM VPI
 138  */
 139 #define IX_ATM_MAX_VPI 255
 140
 141 /**
 142  * @def IX_ATM_MAX_VCI
 143  * @brief Maximum value of an ATM VCI
 144  */
 145 #define IX_ATM_MAX_VCI 65535
 146
 147  /**
 148  * @def IX_ATM_MAX_NUM_AAL_VCS
 149  * @brief Maximum number of active AAL5/AAL0 VCs in the system
 150  */
 151 #define IX_ATM_MAX_NUM_AAL_VCS 32
 152
 153 /**
 154  * @def IX_ATM_MAX_NUM_VC
 155  * @brief Maximum number of active AAL5/AAL0 VCs in the system
 156  * The use of this macro is depreciated, it is retained for
 157  * backward compatiblity. For current software release
 158  * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
 159  */
 160 #define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
 161
 162
 163
 164 /**
 165  * @def IX_ATM_MAX_NUM_OAM_TX_VCS
 166  * @brief Maximum number of active OAM Tx VCs in the system,
 167  *        1 OAM VC per port
 168  */
 169 #define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
 170
 171 /**
 172  * @def IX_ATM_MAX_NUM_OAM_RX_VCS
 173  * @brief Maximum number of active OAM Rx VCs in the system,
 174  *        1 OAM VC shared accross all ports
 175  */
 176 #define IX_ATM_MAX_NUM_OAM_RX_VCS 1
 177
 178 /**
 179  * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
 180  * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
 181  */
 182 #define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
 183
 184 /**
 185  * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
 186  * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
 187  */
 188 #define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
 189
 190 /**
 191  *  @def IX_ATM_IDLE_CELLS_CONNID
 192  *  @brief VC Id used to indicate idle cells in the returned schedule table.
 193  */
 194 #define IX_ATM_IDLE_CELLS_CONNID 0
 195
 196
 197 /**
 198  *  @def IX_ATM_CELL_HEADER_VCI_GET
 199  *  @brief get the VCI field from a cell header
 200  */
 201 #define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
 202     (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
 203
 204 /**
 205  *  @def IX_ATM_CELL_HEADER_VPI_GET
 206  *  @brief get the VPI field from a cell header
 207  */
 208 #define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
 209     (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
 210
 211 /**
 212  *  @def IX_ATM_CELL_HEADER_PTI_GET
 213  *  @brief get the PTI field from a cell header
 214  */
 215 #define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
 216     ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
 217
 218 /**
 219  * @typedef IxAtmCellHeader
 220  *
 221  * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
 222  */
 223 typedef unsigned int IxAtmCellHeader;
 224
 225
 226 /**
 227  * @enum IxAtmServiceCategory
 228  *
 229  * @brief Enumerated type representing available ATM service categories.
 230  *   For more informatoin on these categories, see "Traffic Management
 231  *   Specification" v4.1, published by the ATM Forum -
 232  *   http://www.atmforum.com
 233  */
 234 typedef enum
 235 {
 236     IX_ATM_CBR,    /**< Constant Bit Rate */
 237     IX_ATM_RTVBR,  /**< Real Time Variable Bit Rate */
 238     IX_ATM_VBR,    /**< Variable Bit Rate */
 239     IX_ATM_UBR,    /**< Unspecified Bit Rate */
 240     IX_ATM_ABR     /**< Available Bit Rate (not supported) */
 241
 242 } IxAtmServiceCategory;
 243
 244 /**
 245  *
 246  * @enum IxAtmRxQueueId
 247  *
 248  * @brief Rx Queue Type for RX traffic
 249  *
 250  * IxAtmRxQueueId defines the queues involved for receiving data.
 251  *
 252  * There are two queues to facilitate prioritisation handling
 253  * and processing the 2 queues with different algorithms and
 254  * constraints
 255  *
 256  * e.g. : one queue can carry voice (or time-critical traffic), the
 257  * other queue can carry non-voice traffic
 258  *
 259  */
 260 typedef enum
 261 {
 262     IX_ATM_RX_A = 0,      /**< RX queue A */
 263     IX_ATM_RX_B,          /**< RX queue B */
 264     IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
 265 } IxAtmRxQueueId;
 266
 267 /**
 268  * @brief Structure describing an ATM traffic contract for a Virtual
 269  *         Connection (VC).
 270  *
 271  * Structure is used to specify the requested traffic contract for a
 272  * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
 273  * interface.
 274  *
 275  * These parameters are defined by the ATM forum working group
 276  * (http://www.atmforum.com).
 277  *
 278  * @note Typical values for a voice channel 64 Kbit/s
 279  * - atmService @a IX_ATM_RTVBR
 280  * - pcr   400  (include IP overhead, and AAL5 trailer)
 281  * - cdvt  5000000 (5 ms)
 282  * - scr = pcr
 283  *
 284  * @note Typical values for a data channel 800 Kbit/s
 285  * - atmService @a IX_ATM_UBR
 286  * - pcr   1962  (include IP overhead, and AAL5 trailer)
 287  * - cdvt  5000000 (5 ms)
 288  *
 289  */
 290 typedef struct
 291 {
 292     IxAtmServiceCategory atmService; /**< ATM service category */
 293     unsigned pcr;   /**< Peak Cell Rate - cells per second */
 294     unsigned cdvt;  /**< Cell Delay Variation Tolerance - in nanoseconds */
 295     unsigned scr;   /**< Sustained Cell Rate - cells per second */
 296     unsigned mbs;   /**< Max Burst Size - cells */
 297     unsigned mcr;   /**< Minimum Cell Rate - cells per second */
 298     unsigned mfs;   /**< Max Frame Size - cells */
 299 } IxAtmTrafficDescriptor;
 300
 301 /**
 302  * @typedef IxAtmConnId
 303  *
 304  * @brief ATM VC data connection identifier.
 305  *
 306  * This is is generated by IxAtmdAcc when a successful connection is
 307  * made on a VC. The is the ID by which IxAtmdAcc knows an active
 308  * VC and should be used in IxAtmdAcc API calls to reference a
 309  * specific VC.
 310  */
 311 typedef unsigned int IxAtmConnId;
 312
 313 /**
 314  * @typedef IxAtmSchedulerVcId
 315  *
 316  * @brief ATM VC scheduling connection identifier.
 317  *
 318  * This id is generated and used by ATM Tx controller, generally
 319  * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
 320  * will request one of these Ids whenever a data connection on
 321  * a Tx VC is requested. This ID will be used in callbacks to
 322  * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
 323  * particular VC.
 324  */
 325 typedef int IxAtmSchedulerVcId;
 326
 327 /**
 328  * @typedef IxAtmNpeRxVcId
 329  *
 330  * @brief ATM Rx VC identifier used by the ATM Npe.
 331  *
 332  * This Id is generated by IxAtmdAcc when a successful data connection
 333  * is made on a rx VC.
 334  */
 335 typedef unsigned int IxAtmNpeRxVcId;
 336
 337 /**
 338  * @brief ATM Schedule Table entry
 339  *
 340  * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
 341  * IxAtmdAcc about the data to transmit (in term of cells per VC)
 342  *
 343  * This structure defines
 344  * @li the number of cells to be transmitted (numberOfCells)
 345  * @li the VC connection to be used for transmission (connId).
 346  *
 347  * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
 348  * corresponding number of idle cells will be transmitted to the hardware.
 349  *
 350  */
 351 typedef struct
 352 {
 353     IxAtmConnId connId; /**< connection Id
 354                  *
 355                  * Identifier of VC from which cells are to be transmitted.
 356                  * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
 357                  * that the system should transmit the specified number
 358                  * of idle cells. Unknown connIds result in the transmission
 359                  * idle cells.
 360                  */
 361     unsigned int numberOfCells; /**< number of cells to transmit
 362                  *
 363                  * The number of contiguous cells to schedule from this VC
 364                  * at this point. The valid range is from 1 to
 365                  * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
 366                  * number can swap over mbufs and pdus. OverSchduling results
 367                  * in the transmission of idle cells.
 368                  */
 369 } IxAtmScheduleTableEntry;
 370
 371 /**
 372  * @brief This structure defines a schedule table which gives details
 373  *         on which data (from which VCs) should be transmitted for a
 374  *         forthcoming period of time for a particular port and the
 375  *         order in which that data should be transmitted.
 376  *
 377  *  The schedule table consists of a series of entries each of which
 378  *  will schedule one or more cells from a particular registered VC.
 379  *  The total number of cells scheduled and the total number of
 380  *  entries in the table are also indicated.
 381  *
 382  */
 383 typedef struct
 384 {
 385     unsigned tableSize;      /**< Number of entries
 386                               *
 387                               * Indicates the total number of
 388                               *   entries in the table.
 389                               */
 390     unsigned totalCellSlots; /**< Number of cells
 391                               *
 392                               * Indicates the total number of ATM
 393                               *   cells which are scheduled by all the
 394                               *   entries in the table.
 395                               */
 396     IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
 397                                      *
 398                                      * Pointer to an array
 399                                      *   containing tableSize entries
 400                                      */
 401 } IxAtmScheduleTable;
 402
 403 #endif /* IXATMTYPES_H */
 404
 405 /**
 406  * @} defgroup IxAtmTypes
 407  */
 408
 409