cpu/ixp/start.S

   1 /* vi: set ts=8 sw=8 noet: */
   2 /*
   3  *  u-boot - Startup Code for XScale IXP
   4  *
   5  * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6  *
   7  * Based on startup code example contained in the
   8  * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9  * samples.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/arch/ixp425.h>
  33
  34 #define MMU_Control_M  0x001    /* Enable MMU */
  35 #define MMU_Control_A  0x002    /* Enable address alignment faults */
  36 #define MMU_Control_C  0x004    /* Enable cache */
  37 #define MMU_Control_W  0x008    /* Enable write-buffer */
  38 #define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  39 #define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  40 #define MMU_Control_L  0x040    /* Compatability: */
  41 #define MMU_Control_B  0x080    /* Enable Big-Endian */
  42 #define MMU_Control_S  0x100    /* Enable system protection */
  43 #define MMU_Control_R  0x200    /* Enable ROM protection */
  44 #define MMU_Control_I  0x1000   /* Enable Instruction cache */
  45 #define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  46 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  47
  48
  49 /*
  50  * Macro definitions
  51  */
  52         /* Delay a bit */
  53         .macro DELAY_FOR cycles, reg0
  54         ldr     \reg0, =\cycles
  55         subs    \reg0, \reg0, #1
  56         subne   pc,  pc, #0xc
  57         .endm
  58
  59         /* wait for coprocessor write complete */
  60         .macro CPWAIT reg
  61         mrc  p15,0,\reg,c2,c0,0
  62         mov  \reg,\reg
  63         sub  pc,pc,#4
  64         .endm
  65
  66 .globl _start
  67 _start: b       reset
  68         ldr     pc, _undefined_instruction
  69         ldr     pc, _software_interrupt
  70         ldr     pc, _prefetch_abort
  71         ldr     pc, _data_abort
  72         ldr     pc, _not_used
  73         ldr     pc, _irq
  74         ldr     pc, _fiq
  75
  76 _undefined_instruction: .word undefined_instruction
  77 _software_interrupt:    .word software_interrupt
  78 _prefetch_abort:        .word prefetch_abort
  79 _data_abort:            .word data_abort
  80 _not_used:              .word not_used
  81 _irq:                   .word irq
  82 _fiq:                   .word fiq
  83
  84         .balignl 16,0xdeadbeef
  85
  86
  87 /*
  88  * Startup Code (reset vector)
  89  *
  90  * do important init only if we don't start from memory!
  91  * - relocate armboot to ram
  92  * - setup stack
  93  * - jump to second stage
  94  */
  95
  96 _TEXT_BASE:
  97         .word   TEXT_BASE
  98
  99 .globl _armboot_start
 100 _armboot_start:
 101         .word _start
 102
 103 /*
 104  * These are defined in the board-specific linker script.
 105  */
 106 .globl _bss_start
 107 _bss_start:
 108         .word __bss_start
 109
 110 .globl _bss_end
 111 _bss_end:
 112         .word _end
 113
 114 #ifdef CONFIG_USE_IRQ
 115 /* IRQ stack memory (calculated at run-time) */
 116 .globl IRQ_STACK_START
 117 IRQ_STACK_START:
 118         .word   0x0badc0de
 119
 120 /* IRQ stack memory (calculated at run-time) */
 121 .globl FIQ_STACK_START
 122 FIQ_STACK_START:
 123         .word 0x0badc0de
 124 #endif
 125
 126 /****************************************************************************/
 127 /*                                                                          */
 128 /* the actual reset code                                                    */
 129 /*                                                                          */
 130 /****************************************************************************/
 131
 132 reset:
 133         /* disable mmu, set big-endian */
 134         mov     r0, #0xf8
 135         mcr     p15, 0, r0, c1, c0, 0
 136         CPWAIT  r0
 137
 138         /* invalidate I & D caches & BTB */
 139         mcr     p15, 0, r0, c7, c7, 0
 140         CPWAIT  r0
 141
 142         /* invalidate I & Data TLB */
 143         mcr     p15, 0, r0, c8, c7, 0
 144         CPWAIT r0
 145
 146         /* drain write and fill buffers */
 147         mcr     p15, 0, r0, c7, c10, 4
 148         CPWAIT  r0
 149
 150         /* disable write buffer coalescing */
 151         mrc     p15, 0, r0, c1, c0, 1
 152         orr     r0, r0, #1
 153         mcr     p15, 0, r0, c1, c0, 1
 154         CPWAIT  r0
 155
 156         /* set EXP CS0 to the optimum timing */
 157         ldr     r1, =CFG_EXP_CS0
 158         ldr     r2, =IXP425_EXP_CS0
 159         str     r1, [r2]
 160
 161         /* make sure flash is visible at 0 */
 162         ldr     r2, =IXP425_EXP_CFG0
 163         ldr     r1, [r2]
 164         orr     r1, r1, #0x80000000
 165         str     r1, [r2]
 166
 167         mov     r1, #CFG_SDR_CONFIG
 168         ldr     r2, =IXP425_SDR_CONFIG
 169         str     r1, [r2]
 170
 171         /* disable refresh cycles */
 172         mov     r1, #0
 173         ldr     r3, =IXP425_SDR_REFRESH
 174         str     r1, [r3]
 175
 176         /* send nop command */
 177         mov     r1, #3
 178         ldr     r4, =IXP425_SDR_IR
 179         str     r1, [r4]
 180         DELAY_FOR 0x4000, r0
 181
 182         /* set SDRAM internal refresh val */
 183         ldr     r1, =CFG_SDRAM_REFRESH_CNT
 184         str     r1, [r3]
 185         DELAY_FOR 0x4000, r0
 186
 187         /* send precharge-all command to close all open banks */
 188         mov     r1, #2
 189         str     r1, [r4]
 190         DELAY_FOR 0x4000, r0
 191
 192         /* provide 8 auto-refresh cycles */
 193         mov     r1, #4
 194         mov     r5, #8
 195 111:    str     r1, [r4]
 196         DELAY_FOR 0x100, r0
 197         subs    r5, r5, #1
 198         bne     111b
 199
 200         /* set mode register in sdram */
 201         mov     r1, #1
 202         str     r1, [r4]
 203         DELAY_FOR 0x4000, r0
 204
 205         /* send normal operation command */
 206         mov     r1, #6
 207         str     r1, [r4]
 208         DELAY_FOR 0x4000, r0
 209
 210         /* copy */
 211         mov     r0, #0
 212         mov     r4, r0
 213         add     r2, r0, #0x40000
 214         mov     r1, #0x10000000
 215         mov     r5, r1
 216
 217     30:
 218         ldr     r3, [r0], #4
 219         str     r3, [r1], #4
 220         cmp     r0, r2
 221         bne     30b
 222
 223         /* invalidate I & D caches & BTB */
 224         mcr     p15, 0, r0, c7, c7, 0
 225         CPWAIT  r0
 226
 227         /* invalidate I & Data TLB */
 228         mcr     p15, 0, r0, c8, c7, 0
 229         CPWAIT r0
 230
 231         /* drain write and fill buffers */
 232         mcr     p15, 0, r0, c7, c10, 4
 233         CPWAIT  r0
 234
 235         /* move flash to 0x50000000 */
 236         ldr     r2, =IXP425_EXP_CFG0
 237         ldr     r1, [r2]
 238         bic     r1, r1, #0x80000000
 239         str     r1, [r2]
 240
 241         nop
 242         nop
 243         nop
 244         nop
 245         nop
 246         nop
 247
 248         /* invalidate I & Data TLB */
 249         mcr     p15, 0, r0, c8, c7, 0
 250         CPWAIT r0
 251
 252         /* enable I cache */
 253         mrc     p15, 0, r0, c1, c0, 0
 254         orr     r0, r0, #MMU_Control_I
 255         mcr     p15, 0, r0, c1, c0, 0
 256         CPWAIT  r0
 257
 258         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 259         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 260         orr     r0,r0,#0x13
 261         msr     cpsr,r0
 262
 263 relocate:                               /* relocate U-Boot to RAM           */
 264         adr     r0, _start              /* r0 <- current position of code   */
 265         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 266         cmp     r0, r1                  /* don't reloc during debug         */
 267         beq     stack_setup
 268
 269         ldr     r2, _armboot_start
 270         ldr     r3, _bss_start
 271         sub     r2, r3, r2              /* r2 <- size of armboot            */
 272         add     r2, r0, r2              /* r2 <- source end address         */
 273
 274 copy_loop:
 275         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 276         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 277         cmp     r0, r2                  /* until source end addreee [r2]    */
 278         ble     copy_loop
 279
 280         /* Set up the stack                                                 */
 281 stack_setup:
 282         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 283         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 284         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 285 #ifdef CONFIG_USE_IRQ
 286         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 287 #endif
 288         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 289
 290 clear_bss:
 291         ldr     r0, _bss_start          /* find start of bss segment        */
 292         add     r0, r0, #4              /* start at first byte of bss       */
 293         ldr     r1, _bss_end            /* stop here                        */
 294         mov     r2, #0x00000000         /* clear                            */
 295
 296 clbss_l:str     r2, [r0]                /* clear loop...                    */
 297         add     r0, r0, #4
 298         cmp     r0, r1
 299         bne     clbss_l
 300
 301         ldr     pc, _start_armboot
 302
 303 _start_armboot: .word start_armboot
 304
 305
 306 /****************************************************************************/
 307 /*                                                                          */
 308 /* Interrupt handling                                                       */
 309 /*                                                                          */
 310 /****************************************************************************/
 311
 312 /* IRQ stack frame                                                          */
 313
 314 #define S_FRAME_SIZE    72
 315
 316 #define S_OLD_R0        68
 317 #define S_PSR           64
 318 #define S_PC            60
 319 #define S_LR            56
 320 #define S_SP            52
 321
 322 #define S_IP            48
 323 #define S_FP            44
 324 #define S_R10           40
 325 #define S_R9            36
 326 #define S_R8            32
 327 #define S_R7            28
 328 #define S_R6            24
 329 #define S_R5            20
 330 #define S_R4            16
 331 #define S_R3            12
 332 #define S_R2            8
 333 #define S_R1            4
 334 #define S_R0            0
 335
 336 #define MODE_SVC 0x13
 337
 338         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 339
 340         .macro  bad_save_user_regs
 341         sub     sp, sp, #S_FRAME_SIZE
 342         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 343         add     r8, sp, #S_PC
 344
 345         ldr     r2, _armboot_start
 346         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 347         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 348         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 349         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 350
 351         add     r5, sp, #S_SP
 352         mov     r1, lr
 353         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 354         mov     r0, sp
 355         .endm
 356
 357
 358         /* use irq_save_user_regs / irq_restore_user_regs for                */
 359         /* IRQ/FIQ handling                                                  */
 360
 361         .macro  irq_save_user_regs
 362         sub     sp, sp, #S_FRAME_SIZE
 363         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 364         add     r8, sp, #S_PC
 365         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 366         str     lr, [r8, #0]                    /* Save calling PC           */
 367         mrs     r6, spsr
 368         str     r6, [r8, #4]                    /* Save CPSR                 */
 369         str     r0, [r8, #8]                    /* Save OLD_R0               */
 370         mov     r0, sp
 371         .endm
 372
 373         .macro  irq_restore_user_regs
 374         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 375         mov     r0, r0
 376         ldr     lr, [sp, #S_PC]                 @ Get PC
 377         add     sp, sp, #S_FRAME_SIZE
 378         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 379         .endm
 380
 381         .macro get_bad_stack
 382         ldr     r13, _armboot_start             @ setup our mode stack
 383         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 384         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 385
 386         str     lr, [r13]                       @ save caller lr / spsr
 387         mrs     lr, spsr
 388         str     lr, [r13, #4]
 389
 390         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 391         msr     spsr_c, r13
 392         mov     lr, pc
 393         movs    pc, lr
 394         .endm
 395
 396         .macro get_irq_stack                    @ setup IRQ stack
 397         ldr     sp, IRQ_STACK_START
 398         .endm
 399
 400         .macro get_fiq_stack                    @ setup FIQ stack
 401         ldr     sp, FIQ_STACK_START
 402         .endm
 403
 404
 405 /****************************************************************************/
 406 /*                                                                          */
 407 /* exception handlers                                                       */
 408 /*                                                                          */
 409 /****************************************************************************/
 410
 411         .align  5
 412 undefined_instruction:
 413         get_bad_stack
 414         bad_save_user_regs
 415         bl      do_undefined_instruction
 416
 417         .align  5
 418 software_interrupt:
 419         get_bad_stack
 420         bad_save_user_regs
 421         bl      do_software_interrupt
 422
 423         .align  5
 424 prefetch_abort:
 425         get_bad_stack
 426         bad_save_user_regs
 427         bl      do_prefetch_abort
 428
 429         .align  5
 430 data_abort:
 431         get_bad_stack
 432         bad_save_user_regs
 433         bl      do_data_abort
 434
 435         .align  5
 436 not_used:
 437         get_bad_stack
 438         bad_save_user_regs
 439         bl      do_not_used
 440
 441 #ifdef CONFIG_USE_IRQ
 442
 443         .align  5
 444 irq:
 445         get_irq_stack
 446         irq_save_user_regs
 447         bl      do_irq
 448         irq_restore_user_regs
 449
 450         .align  5
 451 fiq:
 452         get_fiq_stack
 453         irq_save_user_regs              /* someone ought to write a more    */
 454         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 455         irq_restore_user_regs
 456
 457 #else
 458
 459         .align  5
 460 irq:
 461         get_bad_stack
 462         bad_save_user_regs
 463         bl      do_irq
 464
 465         .align  5
 466 fiq:
 467         get_bad_stack
 468         bad_save_user_regs
 469         bl      do_fiq
 470
 471 #endif
 472
 473 /****************************************************************************/
 474 /*                                                                          */
 475 /* Reset function: Use Watchdog to reset                                    */
 476 /*                                                                          */
 477 /****************************************************************************/
 478
 479         .align  5
 480 .globl reset_cpu
 481
 482 reset_cpu:
 483         ldr     r1, =0x482e
 484         ldr     r2, =IXP425_OSWK
 485         str     r1, [r2]
 486         ldr     r1, =0x0fff
 487         ldr     r2, =IXP425_OSWT
 488         str     r1, [r2]
 489         ldr     r1, =0x5
 490         ldr     r2, =IXP425_OSWE
 491         str     r1, [r2]
 492         b       reset_endless
 493
 494
 495 reset_endless:
 496
 497         b       reset_endless