cpu/mcf52x2/cpu.c

   1 /*
   2  * (C) Copyright 2003
   3  * Josef Baumgartner <josef.baumgartner@telex.de>
   4  *
   5  * MCF5282 additionals
   6  * (C) Copyright 2005
   7  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8  *
   9  * MCF5275 additions
  10  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <watchdog.h>
  33 #include <command.h>
  34 #include <asm/immap.h>
  35 #include <netdev.h>
  36
  37 #ifdef  CONFIG_M5271
  38 /*
  39  * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
  40  * determine which one we are running on, based on the Chip Identification
  41  * Register (CIR).
  42  */
  43 int checkcpu(void)
  44 {
  45         char buf[32];
  46         unsigned short cir;     /* Chip Identification Register */
  47         unsigned short pin;     /* Part identification number */
  48         unsigned char prn;      /* Part revision number */
  49         char *cpu_model;
  50
  51         cir = mbar_readShort(MCF_CCM_CIR);
  52         pin = cir >> MCF_CCM_CIR_PIN_LEN;
  53         prn = cir & MCF_CCM_CIR_PRN_MASK;
  54
  55         switch (pin) {
  56         case MCF_CCM_CIR_PIN_MCF5270:
  57                 cpu_model = "5270";
  58                 break;
  59         case MCF_CCM_CIR_PIN_MCF5271:
  60                 cpu_model = "5271";
  61                 break;
  62         default:
  63                 cpu_model = NULL;
  64                 break;
  65         }
  66
  67         if (cpu_model)
  68                 printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
  69                        cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
  70         else
  71                 printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
  72                        " (PIN: 0x%x) rev. %hu, at %s MHz\n",
  73                        pin, prn, strmhz(buf, CONFIG_SYS_CLK));
  74
  75         return 0;
  76 }
  77
  78 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
  79 {
  80         mbar_writeByte(MCF_RCM_RCR,
  81                        MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
  82         return 0;
  83 };
  84
  85 #if defined(CONFIG_WATCHDOG)
  86 void watchdog_reset(void)
  87 {
  88         mbar_writeShort(MCF_WTM_WSR, 0x5555);
  89         mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
  90 }
  91
  92 int watchdog_disable(void)
  93 {
  94         mbar_writeShort(MCF_WTM_WCR, 0);
  95         return (0);
  96 }
  97
  98 int watchdog_init(void)
  99 {
 100         mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
 101         return (0);
 102 }
 103 #endif                          /* #ifdef CONFIG_WATCHDOG */
 104
 105 #endif
 106
 107 #ifdef  CONFIG_M5272
 108 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 109 {
 110         volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 111
 112         wdp->wdog_wrrr = 0;
 113         udelay(1000);
 114
 115         /* enable watchdog, set timeout to 0 and wait */
 116         wdp->wdog_wrrr = 1;
 117         while (1) ;
 118
 119         /* we don't return! */
 120         return 0;
 121 };
 122
 123 int checkcpu(void)
 124 {
 125         volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 126         uchar msk;
 127         char *suf;
 128
 129         puts("CPU:   ");
 130         msk = (sysctrl->sc_dir > 28) & 0xf;
 131         switch (msk) {
 132         case 0x2:
 133                 suf = "1K75N";
 134                 break;
 135         case 0x4:
 136                 suf = "3K75N";
 137                 break;
 138         default:
 139                 suf = NULL;
 140                 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
 141                 break;
 142         }
 143
 144         if (suf)
 145                 printf("Freescale MCF5272 %s\n", suf);
 146         return 0;
 147 };
 148
 149 #if defined(CONFIG_WATCHDOG)
 150 /* Called by macro WATCHDOG_RESET */
 151 void watchdog_reset(void)
 152 {
 153         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 154         wdt->wdog_wcr = 0;
 155 }
 156
 157 int watchdog_disable(void)
 158 {
 159         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 160
 161         wdt->wdog_wcr = 0;      /* reset watchdog counter */
 162         wdt->wdog_wirr = 0;     /* disable watchdog interrupt */
 163         wdt->wdog_wrrr = 0;     /* disable watchdog timer */
 164
 165         puts("WATCHDOG:disabled\n");
 166         return (0);
 167 }
 168
 169 int watchdog_init(void)
 170 {
 171         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 172
 173         wdt->wdog_wirr = 0;     /* disable watchdog interrupt */
 174
 175         /* set timeout and enable watchdog */
 176         wdt->wdog_wrrr =
 177             ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
 178         wdt->wdog_wcr = 0;      /* reset watchdog counter */
 179
 180         puts("WATCHDOG:enabled\n");
 181         return (0);
 182 }
 183 #endif                          /* #ifdef CONFIG_WATCHDOG */
 184
 185 #endif                          /* #ifdef CONFIG_M5272 */
 186
 187 #ifdef  CONFIG_M5275
 188 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 189 {
 190         volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 191
 192         udelay(1000);
 193
 194         rcm->rcr = RCM_RCR_SOFTRST;
 195
 196         /* we don't return! */
 197         return 0;
 198 };
 199
 200 int checkcpu(void)
 201 {
 202         char buf[32];
 203
 204         printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
 205                         strmhz(buf, CONFIG_SYS_CLK));
 206         return 0;
 207 };
 208
 209
 210 #if defined(CONFIG_WATCHDOG)
 211 /* Called by macro WATCHDOG_RESET */
 212 void watchdog_reset(void)
 213 {
 214         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 215         wdt->wsr = 0x5555;
 216         wdt->wsr = 0xAAAA;
 217 }
 218
 219 int watchdog_disable(void)
 220 {
 221         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 222
 223         wdt->wsr = 0x5555; /* reset watchdog counter */
 224         wdt->wsr = 0xAAAA;
 225         wdt->wcr = 0;   /* disable watchdog timer */
 226
 227         puts("WATCHDOG:disabled\n");
 228         return (0);
 229 }
 230
 231 int watchdog_init(void)
 232 {
 233         volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
 234
 235         wdt->wcr = 0;   /* disable watchdog */
 236
 237         /* set timeout and enable watchdog */
 238         wdt->wmr =
 239                 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
 240         wdt->wsr = 0x5555; /* reset watchdog counter */
 241         wdt->wsr = 0xAAAA;
 242
 243         puts("WATCHDOG:enabled\n");
 244         return (0);
 245 }
 246 #endif                          /* #ifdef CONFIG_WATCHDOG */
 247
 248 #endif                          /* #ifdef CONFIG_M5275 */
 249
 250 #ifdef  CONFIG_M5282
 251 int checkcpu(void)
 252 {
 253         unsigned char resetsource = MCFRESET_RSR;
 254
 255         printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
 256                MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
 257         printf("Reset:%s%s%s%s%s%s%s\n",
 258                (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
 259                (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
 260                (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
 261                (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
 262                (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
 263                (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
 264                (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
 265         return 0;
 266 }
 267
 268 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 269 {
 270         MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 271         return 0;
 272 };
 273 #endif
 274
 275 #ifdef CONFIG_M5249
 276 int checkcpu(void)
 277 {
 278         char buf[32];
 279
 280         printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
 281                strmhz(buf, CONFIG_SYS_CLK));
 282         return 0;
 283 }
 284
 285 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 286 {
 287         /* enable watchdog, set timeout to 0 and wait */
 288         mbar_writeByte(MCFSIM_SYPCR, 0xc0);
 289         while (1) ;
 290
 291         /* we don't return! */
 292         return 0;
 293 };
 294 #endif
 295
 296 #ifdef CONFIG_M5253
 297 int checkcpu(void)
 298 {
 299         char buf[32];
 300
 301         unsigned char resetsource = mbar_readLong(SIM_RSR);
 302         printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
 303                strmhz(buf, CONFIG_SYS_CLK));
 304
 305         if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 306                 printf("Reset:%s%s\n",
 307                        (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
 308                        : "",
 309                        (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
 310                        "");
 311         }
 312         return 0;
 313 }
 314
 315 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
 316 {
 317         /* enable watchdog, set timeout to 0 and wait */
 318         mbar_writeByte(SIM_SYPCR, 0xc0);
 319         while (1) ;
 320
 321         /* we don't return! */
 322         return 0;
 323 };
 324 #endif
 325
 326 #if defined(CONFIG_MCFFEC)
 327 /* Default initializations for MCFFEC controllers.  To override,
 328  * create a board-specific function called:
 329  *      int board_eth_init(bd_t *bis)
 330  */
 331
 332 int cpu_eth_init(bd_t *bis)
 333 {
 334         return mcffec_initialize(bis);
 335 }
 336 #endif