]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mcf52x2/speed.c
3 * Josef Baumgartner <josef.baumgartner@telex.de>
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
29 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR
;
34 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
38 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
39 volatile unsigned long cpll
= mbar2_readLong(MCFSIM_PLLCR
);
42 #ifndef CONFIG_SYS_PLL_BYPASS
45 /* Setup the PLL to run at the specified speed */
46 #ifdef CONFIG_SYS_FAST_CLK
47 pllcr
= 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
49 pllcr
= 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
51 #endif /* CONFIG_M5249 */
54 pllcr
= CONFIG_SYS_PLLCR
;
55 #endif /* CONFIG_M5253 */
57 cpll
= cpll
& 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
58 mbar2_writeLong(MCFSIM_PLLCR
, cpll
); /* Set the PLL to bypass mode (PSTCLK = crystal) */
59 mbar2_writeLong(MCFSIM_PLLCR
, pllcr
); /* set the clock speed */
60 pllcr
^= 0x00000001; /* Set pll bypass to 1 */
61 mbar2_writeLong(MCFSIM_PLLCR
, pllcr
); /* Start locking (pll bypass = 1) */
62 udelay(0x20); /* Wait for a lock ... */
63 #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
65 #endif /* CONFIG_M5249 || CONFIG_M5253 */
67 #if defined(CONFIG_M5275)
68 volatile pll_t
*pll
= (volatile pll_t
*)(MMAP_PLL
);
71 pll
->syncr
= 0x01080000;
72 while (!(pll
->synsr
& FMPLL_SYNSR_LOCK
))
74 pll
->syncr
= 0x01000000;
75 while (!(pll
->synsr
& FMPLL_SYNSR_LOCK
))
79 gd
->cpu_clk
= CONFIG_SYS_CLK
;
80 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
81 gd
->bus_clk
= gd
->cpu_clk
/ 2;
83 gd
->bus_clk
= gd
->cpu_clk
;
87 gd
->i2c1_clk
= gd
->bus_clk
;
88 #ifdef CONFIG_SYS_I2C2_OFFSET
89 gd
->i2c2_clk
= gd
->bus_clk
;