cpu/mcf532x/cpu_init.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * (C) Copyright 2007 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30
  31 #include <asm/immap.h>
  32
  33 /*
  34  * Breath some life into the CPU...
  35  *
  36  * Set up the memory map,
  37  * initialize a bunch of registers,
  38  * initialize the UPM's
  39  */
  40 void cpu_init_f(void)
  41 {
  42         volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  43         volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
  44         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  45         volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  46         volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  47
  48         /* watchdog is enabled by default - disable the watchdog */
  49 #ifndef CONFIG_WATCHDOG
  50         wdog->cr = 0;
  51 #endif
  52
  53         scm1->mpr0 = 0x77777777;
  54         scm2->pacra = 0;
  55         scm2->pacrb = 0;
  56         scm2->pacrc = 0;
  57         scm2->pacrd = 0;
  58         scm2->pacre = 0;
  59         scm2->pacrf = 0;
  60         scm2->pacrg = 0;
  61         scm1->pacrh = 0;
  62
  63         /* Port configuration */
  64         gpio->par_cs = 0;
  65
  66 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  67         fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  68         fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  69         fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  70 #endif
  71
  72 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  73         /* Latch chipselect */
  74         gpio->par_cs |= GPIO_PAR_CS1;
  75         fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  76         fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  77         fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  78 #endif
  79
  80 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  81         gpio->par_cs |= GPIO_PAR_CS2;
  82         fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  83         fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  84         fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  85 #endif
  86
  87 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  88         gpio->par_cs |= GPIO_PAR_CS3;
  89         fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  90         fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  91         fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  92 #endif
  93
  94 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  95         gpio->par_cs |= GPIO_PAR_CS4;
  96         fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  97         fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  98         fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  99 #endif
 100
 101 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
 102         gpio->par_cs |= GPIO_PAR_CS5;
 103         fbcs->csar5 = CONFIG_SYS_CS5_BASE;
 104         fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 105         fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 106 #endif
 107
 108 #ifdef CONFIG_FSL_I2C
 109         gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
 110 #endif
 111
 112         icache_enable();
 113 }
 114
 115 /*
 116  * initialize higher level parts of CPU like timers
 117  */
 118 int cpu_init_r(void)
 119 {
 120         return (0);
 121 }
 122
 123 void uart_port_conf(void)
 124 {
 125         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 126
 127         /* Setup Ports: */
 128         switch (CONFIG_SYS_UART_PORT) {
 129         case 0:
 130                 gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
 131                 break;
 132         case 1:
 133                 gpio->par_uart =
 134                     (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
 135                 break;
 136         case 2:
 137                 gpio->par_timer &= 0x0F;
 138                 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
 139                 break;
 140         }
 141 }