cpu/mcf5445x/dspi.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <spi.h>
  30 #include <malloc.h>
  31
  32 #if defined(CONFIG_CF_DSPI)
  33 #include <asm/immap.h>
  34
  35 void dspi_init(void)
  36 {
  37         volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  38         volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  39
  40         gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
  41             GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
  42             GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
  43             GPIO_PAR_DSPI_SCK_SCK;
  44
  45         dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
  46             DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
  47             DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
  48             DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
  49
  50 #ifdef CONFIG_SYS_DSPI_DCTAR0
  51         dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
  52 #endif
  53 #ifdef CONFIG_SYS_DSPI_DCTAR1
  54         dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
  55 #endif
  56 #ifdef CONFIG_SYS_DSPI_DCTAR2
  57         dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
  58 #endif
  59 #ifdef CONFIG_SYS_DSPI_DCTAR3
  60         dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
  61 #endif
  62 #ifdef CONFIG_SYS_DSPI_DCTAR4
  63         dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
  64 #endif
  65 #ifdef CONFIG_SYS_DSPI_DCTAR5
  66         dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
  67 #endif
  68 #ifdef CONFIG_SYS_DSPI_DCTAR6
  69         dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
  70 #endif
  71 #ifdef CONFIG_SYS_DSPI_DCTAR7
  72         dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
  73 #endif
  74 }
  75
  76 void dspi_tx(int chipsel, u8 attrib, u16 data)
  77 {
  78         volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  79
  80         while ((dspi->dsr & 0x0000F000) >= 4) ;
  81
  82         dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
  83 }
  84
  85 u16 dspi_rx(void)
  86 {
  87         volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  88
  89         while ((dspi->dsr & 0x000000F0) == 0) ;
  90
  91         return (dspi->drfr & 0xFFFF);
  92 }
  93
  94 #if defined(CONFIG_CMD_SPI)
  95 void spi_init_f(void)
  96 {
  97 }
  98
  99 void spi_init_r(void)
 100 {
 101 }
 102
 103 void spi_init(void)
 104 {
 105         dspi_init();
 106 }
 107
 108 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 109                                   unsigned int max_hz, unsigned int mode)
 110 {
 111         struct spi_slave *slave;
 112
 113         slave = malloc(sizeof(struct spi_slave));
 114         if (!slave)
 115                 return NULL;
 116
 117         slave->bus = bus;
 118         slave->cs = cs;
 119
 120         return slave;
 121 }
 122
 123 void spi_free_slave(struct spi_slave *slave)
 124 {
 125         free(slave);
 126 }
 127
 128 int spi_claim_bus(struct spi_slave *slave)
 129 {
 130         return 0;
 131 }
 132
 133 void spi_release_bus(struct spi_slave *slave)
 134 {
 135 }
 136
 137 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 138              void *din, unsigned long flags)
 139 {
 140         static int bWrite = 0;
 141         u8 *spi_rd, *spi_wr;
 142         int len = bitlen >> 3;
 143
 144         spi_rd = (u8 *) din;
 145         spi_wr = (u8 *) dout;
 146
 147         /* command handling */
 148         if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
 149                 switch (*spi_wr) {
 150                 case 0x02:      /* Page Prog */
 151                         bWrite = 1;
 152                         dspi_tx(slave->cs, 0x80, spi_wr[0]);
 153                         dspi_rx();
 154                         dspi_tx(slave->cs, 0x80, spi_wr[1]);
 155                         dspi_rx();
 156                         dspi_tx(slave->cs, 0x80, spi_wr[2]);
 157                         dspi_rx();
 158                         dspi_tx(slave->cs, 0x80, spi_wr[3]);
 159                         dspi_rx();
 160                         return 0;
 161                 case 0x05:      /* Read Status */
 162                         if (len == 4)
 163                                 if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
 164                                     && (spi_wr[3] == 0xFF)) {
 165                                         dspi_tx(slave->cs, 0x80, *spi_wr);
 166                                         dspi_rx();
 167                                 }
 168                         return 0;
 169                 case 0x06:      /* WREN */
 170                         dspi_tx(slave->cs, 0x00, *spi_wr);
 171                         dspi_rx();
 172                         return 0;
 173                 case 0x0B:      /* Fast read */
 174                         if ((len == 5) && (spi_wr[4] == 0)) {
 175                                 dspi_tx(slave->cs, 0x80, spi_wr[0]);
 176                                 dspi_rx();
 177                                 dspi_tx(slave->cs, 0x80, spi_wr[1]);
 178                                 dspi_rx();
 179                                 dspi_tx(slave->cs, 0x80, spi_wr[2]);
 180                                 dspi_rx();
 181                                 dspi_tx(slave->cs, 0x80, spi_wr[3]);
 182                                 dspi_rx();
 183                                 dspi_tx(slave->cs, 0x80, spi_wr[4]);
 184                                 dspi_rx();
 185                         }
 186                         return 0;
 187                 case 0x9F:      /* RDID */
 188                         dspi_tx(slave->cs, 0x80, *spi_wr);
 189                         dspi_rx();
 190                         return 0;
 191                 case 0xD8:      /* Sector erase */
 192                         if (len == 4)
 193                                 if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
 194                                         dspi_tx(slave->cs, 0x80, spi_wr[0]);
 195                                         dspi_rx();
 196                                         dspi_tx(slave->cs, 0x80, spi_wr[1]);
 197                                         dspi_rx();
 198                                         dspi_tx(slave->cs, 0x80, spi_wr[2]);
 199                                         dspi_rx();
 200                                         dspi_tx(slave->cs, 0x00, spi_wr[3]);
 201                                         dspi_rx();
 202                                 }
 203                         return 0;
 204                 }
 205         }
 206
 207         if (bWrite)
 208                 len--;
 209
 210         while (len--) {
 211                 if (dout != NULL) {
 212                         dspi_tx(slave->cs, 0x80, *spi_wr);
 213                         dspi_rx();
 214                         spi_wr++;
 215                 }
 216
 217                 if (din != NULL) {
 218                         dspi_tx(slave->cs, 0x80, 0);
 219                         *spi_rd = dspi_rx();
 220                         spi_rd++;
 221                 }
 222         }
 223
 224         if (flags == SPI_XFER_END) {
 225                 if (bWrite) {
 226                         dspi_tx(slave->cs, 0x00, *spi_wr);
 227                         dspi_rx();
 228                         bWrite = 0;
 229                 } else {
 230                         dspi_tx(slave->cs, 0x00, 0);
 231                         dspi_rx();
 232                 }
 233         }
 234
 235         return 0;
 236 }
 237 #endif                          /* CONFIG_CMD_SPI */
 238
 239 #endif                          /* CONFIG_CF_DSPI */