3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap.h>
30 DECLARE_GLOBAL_DATA_PTR
;
33 * Low Power Divider specifications
35 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
36 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
38 #define CLOCK_PLL_FVCO_MAX 540000000
39 #define CLOCK_PLL_FVCO_MIN 300000000
41 #define CLOCK_PLL_FSYS_MAX 266666666
42 #define CLOCK_PLL_FSYS_MIN 100000000
45 void clock_enter_limp(int lpdiv
)
47 volatile ccm_t
*ccm
= (volatile ccm_t
*)MMAP_CCM
;
50 /* Check bounds of divider */
51 if (lpdiv
< CLOCK_LPD_MIN
)
52 lpdiv
= CLOCK_LPD_MIN
;
53 if (lpdiv
> CLOCK_LPD_MAX
)
54 lpdiv
= CLOCK_LPD_MAX
;
56 /* Round divider down to nearest power of two */
57 for (i
= 0, j
= lpdiv
; j
!= 1; j
>>= 1, i
++) ;
59 /* Apply the divider to the system clock */
60 ccm
->cdr
= (ccm
->cdr
& 0xF0FF) | CCM_CDR_LPDIV(i
);
62 /* Enable Limp Mode */
63 ccm
->misccr
|= CCM_MISCCR_LIMP
;
67 * brief Exit Limp mode
68 * warning The PLL should be set and locked prior to exiting Limp mode
70 void clock_exit_limp(void)
72 volatile ccm_t
*ccm
= (volatile ccm_t
*)MMAP_CCM
;
73 volatile pll_t
*pll
= (volatile pll_t
*)MMAP_PLL
;
76 ccm
->misccr
&= ~CCM_MISCCR_LIMP
;
78 /* Wait for the PLL to lock */
79 while (!(pll
->psr
& PLL_PSR_LOCK
)) ;
83 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
88 volatile ccm_t
*ccm
= (volatile ccm_t
*)MMAP_CCM
;
89 volatile pll_t
*pll
= (volatile pll_t
*)MMAP_PLL
;
90 int pllmult_nopci
[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
91 int pllmult_pci
[] = { 12, 6, 16, 8 };
92 int vco
= 0, bPci
, temp
, fbtemp
, pcrvalue
;
96 #ifdef CONFIG_M54455EVB
97 volatile u8
*cpld
= (volatile u8
*)(CONFIG_SYS_CS2_BASE
+ 3);
101 /* To determine PCI is present or not */
102 if (((ccm
->ccr
& CCM_CCR_360_FBCONFIG_MASK
) == 0x00e0) ||
103 ((ccm
->ccr
& CCM_CCR_360_FBCONFIG_MASK
) == 0x0060)) {
104 pPllmult
= &pllmult_pci
[0];
105 fbpll_mask
= 3; /* 11b */
108 pPllmult
= &pllmult_nopci
[0];
109 fbpll_mask
= 7; /* 111b */
116 #ifdef CONFIG_M54455EVB
117 bootmode
= (*cpld
& 0x03);
120 /* Temporary read from CCR- fixed fb issue, must be the same clock
121 as pci or input clock, causing cpld/fpga read inconsistancy */
122 fbtemp
= pPllmult
[ccm
->ccr
& fbpll_mask
];
124 /* Break down into small pieces, code still in flex bus */
125 pcrvalue
= pll
->pcr
& 0xFFFFF0FF;
127 pcrvalue
|= PLL_PCR_OUTDIV3(temp
);
132 #ifdef CONFIG_M54451EVB
133 /* No external logic to read the bootmode, hard coded from built */
139 /* default value is 16 mul, set to 20 mul */
140 pcrvalue
= (pll
->pcr
& 0x00FFFFFF) | 0x14000000;
142 while ((pll
->psr
& PLL_PSR_LOCK
) != PLL_PSR_LOCK
);
148 vco
= pPllmult
[ccm
->rcon
& fbpll_mask
] * CONFIG_SYS_INPUT_CLKSRC
;
150 if ((vco
< CLOCK_PLL_FVCO_MIN
) || (vco
> CLOCK_PLL_FVCO_MAX
)) {
151 /* invaild range, re-set in PCR */
152 int temp
= ((pll
->pcr
& PLL_PCR_OUTDIV2_MASK
) >> 4) + 1;
155 j
= (pll
->pcr
& 0xFF000000) >> 24;
156 for (i
= j
; i
< 0xFF; i
++) {
157 vco
= i
* CONFIG_SYS_INPUT_CLKSRC
;
158 if (vco
>= CLOCK_PLL_FVCO_MIN
) {
160 if (bus
<= CLOCK_PLL_FSYS_MIN
- MHZ
)
166 pcrvalue
= pll
->pcr
& 0x00FF00FF;
167 fbtemp
= ((i
- 1) << 8) | ((i
- 1) << 12);
168 pcrvalue
|= ((i
<< 24) | fbtemp
);
172 gd
->vco_clk
= vco
; /* Vco clock */
173 } else if (bootmode
== 2) {
175 vco
= ((pll
->pcr
& 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC
;
176 if ((vco
< CLOCK_PLL_FVCO_MIN
) || (vco
> CLOCK_PLL_FVCO_MAX
)) {
178 pcrvalue
= (pll
->pcr
& 0x00FFFFFF);
179 pcrvalue
|= pPllmult
[ccm
->ccr
& fbpll_mask
] << 24;
181 vco
= ((pll
->pcr
& 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC
;
183 gd
->vco_clk
= vco
; /* Vco clock */
184 } else if (bootmode
== 3) {
186 vco
= ((pll
->pcr
& 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC
;
187 gd
->vco_clk
= vco
; /* Vco clock */
190 if ((ccm
->ccr
& CCM_MISCCR_LIMP
) == CCM_MISCCR_LIMP
) {
193 gd
->inp_clk
= CONFIG_SYS_INPUT_CLKSRC
; /* Input clock */
195 temp
= (pll
->pcr
& PLL_PCR_OUTDIV1_MASK
) + 1;
196 gd
->cpu_clk
= vco
/ temp
; /* cpu clock */
198 temp
= ((pll
->pcr
& PLL_PCR_OUTDIV2_MASK
) >> 4) + 1;
199 gd
->bus_clk
= vco
/ temp
; /* bus clock */
201 temp
= ((pll
->pcr
& PLL_PCR_OUTDIV3_MASK
) >> 8) + 1;
202 gd
->flb_clk
= vco
/ temp
; /* FlexBus clock */
206 temp
= ((pll
->pcr
& PLL_PCR_OUTDIV4_MASK
) >> 12) + 1;
207 gd
->pci_clk
= vco
/ temp
; /* PCI clock */
212 #ifdef CONFIG_FSL_I2C
213 gd
->i2c1_clk
= gd
->bus_clk
;