cpu/mips/au1x00_eth.c

   1 /* Only eth0 supported for now
   2  *
   3  * (C) Copyright 2003
   4  * Thomas.Lange@corelatus.se
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #include <config.h>
  25
  26 #ifdef CONFIG_AU1X00
  27
  28 #if defined(CFG_DISCOVER_PHY)
  29 #error "PHY not supported yet"
  30 /* We just assume that we are running 100FD for now */
  31 /* We all use switches, right? ;-) */
  32 #endif
  33
  34 /* I assume ethernet behaves like au1000 */
  35
  36 #ifdef CONFIG_AU1000
  37 /* Base address differ between cpu:s */
  38 #define ETH0_BASE AU1000_ETH0_BASE
  39 #define MAC0_ENABLE AU1000_MAC0_ENABLE
  40 #else
  41 #ifdef CONFIG_AU1100
  42 #define ETH0_BASE AU1100_ETH0_BASE
  43 #define MAC0_ENABLE AU1100_MAC0_ENABLE
  44 #else
  45 #ifdef CONFIG_AU1500
  46 #define ETH0_BASE AU1500_ETH0_BASE
  47 #define MAC0_ENABLE AU1500_MAC0_ENABLE
  48 #else
  49 #ifdef CONFIG_AU1550
  50 #define ETH0_BASE AU1550_ETH0_BASE
  51 #define MAC0_ENABLE AU1550_MAC0_ENABLE
  52 #else
  53 #error "No valid cpu set"
  54 #endif
  55 #endif
  56 #endif
  57 #endif
  58
  59 #include <common.h>
  60 #include <malloc.h>
  61 #include <net.h>
  62 #include <command.h>
  63 #include <asm/io.h>
  64 #include <asm/au1x00.h>
  65
  66 /* Ethernet Transmit and Receive Buffers */
  67 #define DBUF_LENGTH  1520
  68 #define PKT_MAXBUF_SIZE         1518
  69
  70 static char txbuf[DBUF_LENGTH];
  71
  72 static int next_tx;
  73 static int next_rx;
  74
  75 /* 4 rx and 4 tx fifos */
  76 #define NO_OF_FIFOS 4
  77
  78 typedef struct{
  79         u32 status;
  80         u32 addr;
  81         u32 len; /* Only used for tx */
  82         u32 not_used;
  83 } mac_fifo_t;
  84
  85 mac_fifo_t mac_fifo[NO_OF_FIFOS];
  86
  87 #define MAX_WAIT 1000
  88
  89 static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
  90         volatile mac_fifo_t *fifo_tx =
  91                 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
  92         int i;
  93         int res;
  94
  95         /* tx fifo should always be idle */
  96         fifo_tx[next_tx].len = length;
  97         fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
  98         au_sync();
  99
 100         udelay(1);
 101         i=0;
 102         while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
 103                 if(i>MAX_WAIT){
 104                         printf("TX timeout\n");
 105                         break;
 106                 }
 107                 udelay(1);
 108                 i++;
 109         }
 110
 111         /* Clear done bit */
 112         fifo_tx[next_tx].addr = 0;
 113         fifo_tx[next_tx].len = 0;
 114         au_sync();
 115
 116         res = fifo_tx[next_tx].status;
 117
 118         next_tx++;
 119         if(next_tx>=NO_OF_FIFOS){
 120                 next_tx=0;
 121         }
 122         return(res);
 123 }
 124
 125 static int au1x00_recv(struct eth_device* dev){
 126         volatile mac_fifo_t *fifo_rx =
 127                 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 128
 129         int length;
 130         u32 status;
 131
 132         for(;;){
 133                 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
 134                         /* Nothing has been received */
 135                         return(-1);
 136                 }
 137
 138                 status = fifo_rx[next_rx].status;
 139
 140                 length = status&0x3FFF;
 141
 142                 if(status&RX_ERROR){
 143                         printf("Rx error 0x%x\n", status);
 144                 }
 145                 else{
 146                         /* Pass the packet up to the protocol layers. */
 147                         NetReceive(NetRxPackets[next_rx], length - 4);
 148                 }
 149
 150                 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
 151
 152                 next_rx++;
 153                 if(next_rx>=NO_OF_FIFOS){
 154                         next_rx=0;
 155                 }
 156         } /* for */
 157
 158         return(0); /* Does anyone use this? */
 159 }
 160
 161 static int au1x00_init(struct eth_device* dev, bd_t * bd){
 162
 163         volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 164         volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
 165         volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
 166         volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
 167         volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
 168         volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
 169         volatile mac_fifo_t *fifo_tx =
 170                 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 171         volatile mac_fifo_t *fifo_rx =
 172                 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 173         int i;
 174
 175         next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
 176         next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
 177
 178         /* We have to enable clocks before releasing reset */
 179         *macen = MAC_EN_CLOCK_ENABLE;
 180         udelay(10);
 181
 182         /* Enable MAC0 */
 183         /* We have to release reset before accessing registers */
 184         *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
 185                 MAC_EN_RESET1|MAC_EN_RESET2;
 186         udelay(10);
 187
 188         for(i=0;i<NO_OF_FIFOS;i++){
 189                 fifo_tx[i].len = 0;
 190                 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
 191                 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
 192         }
 193
 194         /* Put mac addr in little endian */
 195 #define ea eth_get_dev()->enetaddr
 196         *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
 197         *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
 198                 (ea[1] <<  8) | (ea[0]      ) ;
 199 #undef ea
 200         *mac_mcast_low = 0;
 201         *mac_mcast_high = 0;
 202
 203         /* Make sure the MAC buffer is in the correct endian mode */
 204 #ifdef __LITTLE_ENDIAN
 205         *mac_ctrl = MAC_FULL_DUPLEX;
 206         udelay(1);
 207         *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 208 #else
 209         *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
 210         udelay(1);
 211         *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 212 #endif
 213
 214         return(1);
 215 }
 216
 217 static void au1x00_halt(struct eth_device* dev){
 218 }
 219
 220 int au1x00_enet_initialize(bd_t *bis){
 221         struct eth_device* dev;
 222
 223         dev = (struct eth_device*) malloc(sizeof *dev);
 224         memset(dev, 0, sizeof *dev);
 225
 226         sprintf(dev->name, "Au1X00 ETHERNET");
 227         dev->iobase = 0;
 228         dev->priv   = 0;
 229         dev->init   = au1x00_init;
 230         dev->halt   = au1x00_halt;
 231         dev->send   = au1x00_send;
 232         dev->recv   = au1x00_recv;
 233
 234         eth_register(dev);
 235
 236         return 1;
 237 }
 238
 239 #if (CONFIG_COMMANDS & CFG_CMD_MII)
 240 int  miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
 241 {
 242         volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
 243         volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
 244         u32 mii_control;
 245         unsigned int timedout = 20;
 246
 247         while (*mii_control_reg & MAC_MII_BUSY) {
 248                 udelay(1000);
 249                 if (--timedout == 0) {
 250                         printf("au1x00_eth: miiphy_read busy timeout!!\n");
 251                         return -1;
 252                 }
 253         }
 254
 255         mii_control = MAC_SET_MII_SELECT_REG(reg) |
 256                 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
 257
 258         *mii_control_reg = mii_control;
 259
 260         timedout = 20;
 261         while (*mii_control_reg & MAC_MII_BUSY) {
 262                 udelay(1000);
 263                 if (--timedout == 0) {
 264                         printf("au1x00_eth: miiphy_read busy timeout!!\n");
 265                         return -1;
 266                 }
 267         }
 268         *value = *mii_data_reg;
 269         return 0;
 270 }
 271
 272 int  miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
 273 {
 274         volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
 275         volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
 276         u32 mii_control;
 277         unsigned int timedout = 20;
 278
 279         while (*mii_control_reg & MAC_MII_BUSY) {
 280                 udelay(1000);
 281                 if (--timedout == 0) {
 282                         printf("au1x00_eth: miiphy_write busy timeout!!\n");
 283                         return;
 284                 }
 285         }
 286
 287         mii_control = MAC_SET_MII_SELECT_REG(reg) |
 288                 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
 289
 290         *mii_data_reg = value;
 291         *mii_control_reg = mii_control;
 292         return 0;
 293 }
 294 #endif  /* CONFIG_COMMANDS & CFG_CMD_MII */
 295
 296 #endif /* CONFIG_AU1X00 */