cpu/mpc512x/pci.c

   1 /*
   2  * Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #include <asm/io.h>
  27 #include <asm/mmu.h>
  28 #include <asm/global_data.h>
  29 #include <pci.h>
  30 #if defined(CONFIG_OF_LIBFDT)
  31 #include <libfdt.h>
  32 #include <fdt_support.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* System RAM mapped to PCI space */
  38 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  39 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  40
  41 static struct pci_controller pci_hose;
  42
  43
  44 /**************************************************************************
  45  * pci_init_board()
  46  *
  47  */
  48 void
  49 pci_init_board(void)
  50 {
  51         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  52         volatile law512x_t *pci_law;
  53         volatile pot512x_t *pci_pot;
  54         volatile pcictrl512x_t *pci_ctrl;
  55         volatile pciconf512x_t *pci_conf;
  56         u16 reg16;
  57         u32 reg32;
  58         u32 dev;
  59         int i;
  60         struct pci_controller *hose;
  61
  62         /* Set PCI divider for 33MHz */
  63         reg32 = in_be32(&im->clk.scfr[0]);
  64         reg32 &= ~(SCFR1_PCI_DIV_MASK);
  65         reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
  66         out_be32(&im->clk.scfr[0], reg32);
  67
  68         clrsetbits_be32(&im->clk.scfr[0],
  69                         SCFR1_PCI_DIV_MASK,
  70                         SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
  71         );
  72
  73         pci_law = im->sysconf.pcilaw;
  74         pci_pot = im->ios.pot;
  75         pci_ctrl = &im->pci_ctrl;
  76         pci_conf = &im->pci_conf;
  77
  78         hose = &pci_hose;
  79
  80         /*
  81          * Release PCI RST Output signal
  82          */
  83         out_be32(&pci_ctrl->gcr, 0);
  84         udelay(2000);
  85         out_be32(&pci_ctrl->gcr, 1);
  86
  87         /* We need to wait at least a 1sec based on PCI specs */
  88         for (i = 0; i < 1000; i++)
  89                 udelay(1000);
  90
  91         /*
  92          * Configure PCI Local Access Windows
  93          */
  94         out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
  95         out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
  96
  97         out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
  98         out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
  99
 100         /*
 101          * Configure PCI Outbound Translation Windows
 102          */
 103
 104         /* PCI mem space - prefetch */
 105         out_be32(&pci_pot[0].potar,
 106                 (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
 107         out_be32(&pci_pot[0].pobar,
 108                 (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
 109         out_be32(&pci_pot[0].pocmr,
 110                 POCMR_EN | POCMR_PRE | POCMR_CM_256M);
 111
 112         /* PCI IO space */
 113         out_be32(&pci_pot[1].potar,
 114                 (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
 115         out_be32(&pci_pot[1].pobar,
 116                 (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
 117         out_be32(&pci_pot[1].pocmr,
 118                 POCMR_EN | POCMR_IO | POCMR_CM_16M);
 119
 120         /* PCI mmio - non-prefetch mem space */
 121         out_be32(&pci_pot[2].potar,
 122                 (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
 123         out_be32(&pci_pot[2].pobar,
 124                 (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
 125         out_be32(&pci_pot[2].pocmr,
 126                 POCMR_EN | POCMR_CM_256M);
 127
 128         /*
 129          * Configure PCI Inbound Translation Windows
 130          */
 131
 132         /* we need RAM mapped to PCI space for the devices to
 133          * access main memory */
 134         out_be32(&pci_ctrl[0].pitar1, 0x0);
 135         out_be32(&pci_ctrl[0].pibar1, 0x0);
 136         out_be32(&pci_ctrl[0].piebar1, 0x0);
 137         out_be32(&pci_ctrl[0].piwar1,
 138                 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 139                 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
 140
 141         hose->first_busno = 0;
 142         hose->last_busno = 0xff;
 143
 144         /* PCI memory prefetch space */
 145         pci_set_region(hose->regions + 0,
 146                        CONFIG_SYS_PCI_MEM_BASE,
 147                        CONFIG_SYS_PCI_MEM_PHYS,
 148                        CONFIG_SYS_PCI_MEM_SIZE,
 149                        PCI_REGION_MEM|PCI_REGION_PREFETCH);
 150
 151         /* PCI memory space */
 152         pci_set_region(hose->regions + 1,
 153                        CONFIG_SYS_PCI_MMIO_BASE,
 154                        CONFIG_SYS_PCI_MMIO_PHYS,
 155                        CONFIG_SYS_PCI_MMIO_SIZE,
 156                        PCI_REGION_MEM);
 157
 158         /* PCI IO space */
 159         pci_set_region(hose->regions + 2,
 160                        CONFIG_SYS_PCI_IO_BASE,
 161                        CONFIG_SYS_PCI_IO_PHYS,
 162                        CONFIG_SYS_PCI_IO_SIZE,
 163                        PCI_REGION_IO);
 164
 165         /* System memory space */
 166         pci_set_region(hose->regions + 3,
 167                        CONFIG_PCI_SYS_MEM_BUS,
 168                        CONFIG_PCI_SYS_MEM_PHYS,
 169                        gd->ram_size,
 170                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 171
 172         hose->region_count = 4;
 173
 174         pci_setup_indirect(hose,
 175                            (CONFIG_SYS_IMMR + 0x8300),
 176                            (CONFIG_SYS_IMMR + 0x8304));
 177
 178         pci_register_hose(hose);
 179
 180         /*
 181          * Write to Command register
 182          */
 183         reg16 = 0xff;
 184         dev = PCI_BDF(hose->first_busno, 0, 0);
 185         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
 186         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 187         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 188
 189         /*
 190          * Clear non-reserved bits in status register.
 191          */
 192         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 193         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 194         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 195
 196 #ifdef CONFIG_PCI_SCAN_SHOW
 197         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 198 #endif
 199         /*
 200          * Hose scan.
 201          */
 202         hose->last_busno = pci_hose_scan(hose);
 203 }
 204
 205 #if defined(CONFIG_OF_LIBFDT)
 206 void ft_pci_setup(void *blob, bd_t *bd)
 207 {
 208         int nodeoffset;
 209         int tmp[2];
 210         const char *path;
 211
 212         nodeoffset = fdt_path_offset(blob, "/aliases");
 213         if (nodeoffset >= 0) {
 214                 path = fdt_getprop(blob, nodeoffset, "pci", NULL);
 215                 if (path) {
 216                         tmp[0] = cpu_to_be32(pci_hose.first_busno);
 217                         tmp[1] = cpu_to_be32(pci_hose.last_busno);
 218                         do_fixup_by_path(blob, path, "bus-range",
 219                                 &tmp, sizeof(tmp), 1);
 220
 221                         tmp[0] = cpu_to_be32(gd->pci_clk);
 222                         do_fixup_by_path(blob, path, "clock-frequency",
 223                                 &tmp, sizeof(tmp[0]), 1);
 224                 }
 225         }
 226 }
 227 #endif /* CONFIG_OF_LIBFDT */