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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mpc512x/speed.c
2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Based on the MPC83xx code.
31 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 static int spmf_mult
[] = {
42 static int cpmf_mult
[][2] = {
43 {0, 1}, {0, 1}, /* 0 and 1 are not valid */
47 {0, 1}, {0, 1}, /* and all above 7 are not valid too */
53 static int sys_dividors
[][2] = {
54 {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
55 {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
56 {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
57 {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
58 {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
59 {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
60 {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
65 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
71 u32 ref_clk
= CONFIG_SYS_MPC512X_CLKIN
;
79 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
82 spmf
= (im
->clk
.spmr
& SPMR_SPMF
) >> SPMR_SPMF_SHIFT
;
83 spll
= ref_clk
* spmf_mult
[spmf
];
85 sys_div
= (im
->clk
.scfr
[1] & SCFR2_SYS_DIV
) >> SCFR2_SYS_DIV_SHIFT
;
86 sys_clk
= (spll
* sys_dividors
[sys_div
][1]) / sys_dividors
[sys_div
][0];
88 csb_clk
= sys_clk
/ 2;
90 cpmf
= (im
->clk
.spmr
& SPMR_CPMF
) >> SPMR_CPMF_SHIFT
;
91 core_clk
= (csb_clk
* cpmf_mult
[cpmf
][0]) / cpmf_mult
[cpmf
][1];
93 ips_div
= (im
->clk
.scfr
[0] & SCFR1_IPS_DIV_MASK
) >> SCFR1_IPS_DIV_SHIFT
;
95 ips_clk
= csb_clk
/ ips_div
;
97 /* in case we cannot get a sane IPS divisor, fail gracefully */
100 pci_div
= (im
->clk
.scfr
[0] & SCFR1_PCI_DIV_MASK
) >> SCFR1_PCI_DIV_SHIFT
;
102 pci_clk
= csb_clk
/ pci_div
;
104 /* in case we cannot get a sane IPS divisor, fail gracefully */
108 gd
->ips_clk
= ips_clk
;
109 gd
->pci_clk
= pci_clk
;
110 gd
->csb_clk
= csb_clk
;
111 gd
->cpu_clk
= core_clk
;
112 gd
->bus_clk
= csb_clk
;
117 /********************************************
119 * return system bus freq in Hz
120 *********************************************/
121 ulong
get_bus_freq (ulong dummy
)
126 int do_clocks (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
128 printf("Clock configuration:\n");
129 printf(" CPU: %4ld MHz\n", gd
->cpu_clk
/ 1000000);
130 printf(" Coherent System Bus: %4d MHz\n", gd
->csb_clk
/ 1000000);
131 printf(" IPS Bus: %4d MHz\n", gd
->ips_clk
/ 1000000);
132 printf(" PCI: %4d MHz\n", gd
->pci_clk
/ 1000000);
133 printf(" DDR: %4d MHz\n", 2 * gd
->csb_clk
/ 1000000);
137 U_BOOT_CMD(clocks
, 1, 0, do_clocks
,
138 "clocks - print clock configuration\n",
142 int prt_mpc512x_clks (void)
144 do_clocks (NULL
, 0, 0, NULL
);