cpu/mpc512x/speed.c

   1 /*
   2  * (C) Copyright 2000-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  *
  25  * Based on the MPC83xx code.
  26  */
  27
  28 #include <common.h>
  29 #include <mpc512x.h>
  30 #include <command.h>
  31 #include <asm/processor.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 static int spmf_mult[] = {
  36         68, 1, 12, 16,
  37         20, 24, 28, 32,
  38         36, 40, 44, 48,
  39         52, 56, 60, 64
  40 };
  41
  42 static int cpmf_mult[][2] = {
  43         {0, 1}, {0, 1}, /* 0 and 1 are not valid */
  44         {1, 1}, {3, 2},
  45         {2, 1}, {5, 2},
  46         {3, 1}, {7, 2},
  47         {0, 1}, {0, 1}, /* and all above 7 are not valid too */
  48         {0, 1}, {0, 1},
  49         {0, 1}, {0, 1},
  50         {0, 1}, {0, 1}
  51 };
  52
  53 static int sys_dividors[][2] = {
  54         {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
  55         {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
  56         {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
  57         {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
  58         {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
  59         {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
  60         {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
  61 };
  62
  63 int get_clocks (void)
  64 {
  65         volatile immap_t *im = (immap_t *) CFG_IMMR;
  66         u8 spmf;
  67         u8 cpmf;
  68         u8 sys_div;
  69         u8 ips_div;
  70         u32 ref_clk = CFG_MPC512X_CLKIN;
  71         u32 spll;
  72         u32 sys_clk;
  73         u32 core_clk;
  74         u32 csb_clk;
  75         u32 ips_clk;
  76
  77         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  78                 return -1;
  79
  80         spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  81         spll = ref_clk * spmf_mult[spmf];
  82
  83         sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
  84         sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
  85
  86         csb_clk = sys_clk / 2;
  87
  88         cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
  89         core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
  90
  91         ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
  92         if (ips_div != 0) {
  93                 ips_clk = csb_clk / ips_div;
  94         } else {
  95                 /* in case we cannot get a sane IPS divisor, fail gracefully */
  96                 ips_clk = 0;
  97         }
  98
  99         gd->ipb_clk = ips_clk;
 100         gd->csb_clk = csb_clk;
 101         gd->cpu_clk = core_clk;
 102         gd->bus_clk = csb_clk;
 103         return 0;
 104
 105 }
 106
 107 /********************************************
 108  * get_bus_freq
 109  * return system bus freq in Hz
 110  *********************************************/
 111 ulong get_bus_freq (ulong dummy)
 112 {
 113         return gd->csb_clk;
 114 }
 115
 116 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 117 {
 118         printf ("Clock configuration:\n");
 119         printf ("  CPU:                 %4d MHz\n", gd->cpu_clk / 1000000);
 120         printf ("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 121         printf ("  IPS Bus:             %4d MHz\n", gd->ipb_clk / 1000000);
 122         printf ("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
 123         return 0;
 124 }
 125
 126 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 127         "clocks  - print clock configuration\n",
 128         "    clocks\n"
 129 );
 130
 131 int prt_mpc512x_clks (void)
 132 {
 133         do_clocks (NULL, 0, 0, NULL);
 134         return (0);
 135 }