]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mpc5xxx/fec.c
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
17 DECLARE_GLOBAL_DATA_PTR
;
19 /* #define DEBUG 0x28 */
21 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
22 defined(CONFIG_MPC5xxx_FEC)
24 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
25 #error "CONFIG_MII has to be defined!"
29 static void tfifo_print(char *devname
, mpc5xxx_fec_priv
*fec
);
30 static void rfifo_print(char *devname
, mpc5xxx_fec_priv
*fec
);
34 static uint32
local_crc32(char *string
, unsigned int crc_value
, int len
);
38 uint8 data
[1500]; /* actual data */
39 int length
; /* actual length */
40 int used
; /* buffer in use or not */
41 uint8 head
[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
44 int fec5xxx_miiphy_read(char *devname
, uint8 phyAddr
, uint8 regAddr
, uint16
* retVal
);
45 int fec5xxx_miiphy_write(char *devname
, uint8 phyAddr
, uint8 regAddr
, uint16 data
);
47 /********************************************************************/
49 static void mpc5xxx_fec_phydump (char *devname
)
52 uint8 phyAddr
= CONFIG_PHY_ADDR
;
54 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
65 for (i
= 0; i
< 32; i
++) {
67 miiphy_read(devname
, phyAddr
, i
, &phyStatus
);
68 printf("Mii reg %d: 0x%04x\n", i
, phyStatus
);
74 /********************************************************************/
75 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv
*fec
)
81 for (ix
= 0; ix
< FEC_RBD_NUM
; ix
++) {
83 data
= (char *)malloc(FEC_MAX_PKT_SIZE
);
85 printf ("RBD INIT FAILED\n");
88 fec
->rbdBase
[ix
].dataPointer
= (uint32
)data
;
90 fec
->rbdBase
[ix
].status
= FEC_RBD_EMPTY
;
91 fec
->rbdBase
[ix
].dataLength
= 0;
96 * have the last RBD to close the ring
98 fec
->rbdBase
[ix
- 1].status
|= FEC_RBD_WRAP
;
104 /********************************************************************/
105 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv
*fec
)
109 for (ix
= 0; ix
< FEC_TBD_NUM
; ix
++) {
110 fec
->tbdBase
[ix
].status
= 0;
114 * Have the last TBD to close the ring
116 fec
->tbdBase
[ix
- 1].status
|= FEC_TBD_WRAP
;
119 * Initialize some indices
122 fec
->usedTbdIndex
= 0;
123 fec
->cleanTbdNum
= FEC_TBD_NUM
;
126 /********************************************************************/
127 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv
*fec
, volatile FEC_RBD
* pRbd
)
130 * Reset buffer descriptor as empty
132 if ((fec
->rbdIndex
) == (FEC_RBD_NUM
- 1))
133 pRbd
->status
= (FEC_RBD_WRAP
| FEC_RBD_EMPTY
);
135 pRbd
->status
= FEC_RBD_EMPTY
;
137 pRbd
->dataLength
= 0;
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO
);
147 fec
->rbdIndex
= (fec
->rbdIndex
+ 1) % FEC_RBD_NUM
;
150 /********************************************************************/
151 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv
*fec
)
153 volatile FEC_TBD
*pUsedTbd
;
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec
->cleanTbdNum
, fec
->usedTbdIndex
);
161 * process all the consumed TBDs
163 while (fec
->cleanTbdNum
< FEC_TBD_NUM
) {
164 pUsedTbd
= &fec
->tbdBase
[fec
->usedTbdIndex
];
165 if (pUsedTbd
->status
& FEC_TBD_READY
) {
167 printf("Cannot clean TBD %d, in use\n", fec
->cleanTbdNum
);
173 * clean this buffer descriptor
175 if (fec
->usedTbdIndex
== (FEC_TBD_NUM
- 1))
176 pUsedTbd
->status
= FEC_TBD_WRAP
;
178 pUsedTbd
->status
= 0;
181 * update some indeces for a correct handling of the TBD ring
184 fec
->usedTbdIndex
= (fec
->usedTbdIndex
+ 1) % FEC_TBD_NUM
;
188 /********************************************************************/
189 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv
*fec
, char *mac
)
191 uint8 currByte
; /* byte for which to compute the CRC */
192 int byte
; /* loop - counter */
193 int bit
; /* loop - counter */
194 uint32 crc
= 0xffffffff; /* initial value */
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
211 for (byte
= 0; byte
< 6; byte
++) {
212 currByte
= mac
[byte
];
213 for (bit
= 0; bit
< 8; bit
++) {
214 if ((currByte
& 0x01) ^ (crc
& 0x01)) {
216 crc
= crc
^ 0xedb88320;
227 * Set individual hash table register
230 fec
->eth
->iaddr1
= (1 << (crc
- 32));
231 fec
->eth
->iaddr2
= 0;
233 fec
->eth
->iaddr1
= 0;
234 fec
->eth
->iaddr2
= (1 << crc
);
238 * Set physical address
240 fec
->eth
->paddr1
= (mac
[0] << 24) + (mac
[1] << 16) + (mac
[2] << 8) + mac
[3];
241 fec
->eth
->paddr2
= (mac
[4] << 24) + (mac
[5] << 16) + 0x8808;
244 /********************************************************************/
245 static int mpc5xxx_fec_init(struct eth_device
*dev
, bd_t
* bis
)
247 mpc5xxx_fec_priv
*fec
= (mpc5xxx_fec_priv
*)dev
->priv
;
248 struct mpc5xxx_sdma
*sdma
= (struct mpc5xxx_sdma
*)MPC5XXX_SDMA
;
251 printf ("mpc5xxx_fec_init... Begin\n");
255 * Initialize RxBD/TxBD rings
257 mpc5xxx_fec_rbd_init(fec
);
258 mpc5xxx_fec_tbd_init(fec
);
261 * Clear FEC-Lite interrupt event register(IEVENT)
263 fec
->eth
->ievent
= 0xffffffff;
266 * Set interrupt mask register
268 fec
->eth
->imask
= 0x00000000;
271 * Set FEC-Lite receive control register(R_CNTRL):
273 if (fec
->xcv_type
== SEVENWIRE
) {
275 * Frame length=1518; 7-wire mode
277 fec
->eth
->r_cntrl
= 0x05ee0020; /*0x05ee0000;FIXME */
280 * Frame length=1518; MII mode;
282 fec
->eth
->r_cntrl
= 0x05ee0024; /*0x05ee0004;FIXME */
285 fec
->eth
->x_cntrl
= 0x00000000; /* half-duplex, heartbeat disabled */
286 if (fec
->xcv_type
!= SEVENWIRE
) {
288 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
289 * and do not drop the Preamble.
291 fec
->eth
->mii_speed
= (((gd
->ipb_clk
>> 20) / 5) << 1); /* No MII for 7-wire mode */
295 * Set Opcode/Pause Duration Register
297 fec
->eth
->op_pause
= 0x00010020; /*FIXME 0xffff0020; */
300 * Set Rx FIFO alarm and granularity value
302 fec
->eth
->rfifo_cntrl
= 0x0c000000
303 | (fec
->eth
->rfifo_cntrl
& ~0x0f000000);
304 fec
->eth
->rfifo_alarm
= 0x0000030c;
306 if (fec
->eth
->rfifo_status
& 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
312 * Set Tx FIFO granularity value
314 fec
->eth
->tfifo_cntrl
= 0x0c000000
315 | (fec
->eth
->tfifo_cntrl
& ~0x0f000000);
317 printf("tfifo_status: 0x%08x\n", fec
->eth
->tfifo_status
);
318 printf("tfifo_alarm: 0x%08x\n", fec
->eth
->tfifo_alarm
);
322 * Set transmit fifo watermark register(X_WMRK), default = 64
324 fec
->eth
->tfifo_alarm
= 0x00000080;
325 fec
->eth
->x_wmrk
= 0x2;
328 * Set individual address filter for unicast address
329 * and set physical address registers.
331 mpc5xxx_fec_set_hwaddr(fec
, (char *)dev
->enetaddr
);
334 * Set multicast address filter
336 fec
->eth
->gaddr1
= 0x00000000;
337 fec
->eth
->gaddr2
= 0x00000000;
340 * Turn ON cheater FSM: ????
342 fec
->eth
->xmit_fsm
= 0x03000000;
344 #if defined(CONFIG_MPC5200)
346 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
347 * work w/ the current receive task.
349 sdma
->PtdCntrl
|= 0x00000001;
353 * Set priority of different initiators
355 sdma
->IPR0
= 7; /* always */
356 sdma
->IPR3
= 6; /* Eth RX */
357 sdma
->IPR4
= 5; /* Eth Tx */
360 * Clear SmartDMA task interrupt pending bits
362 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO
);
365 * Initialize SmartDMA parameters stored in SRAM
367 *(volatile int *)FEC_TBD_BASE
= (int)fec
->tbdBase
;
368 *(volatile int *)FEC_RBD_BASE
= (int)fec
->rbdBase
;
369 *(volatile int *)FEC_TBD_NEXT
= (int)fec
->tbdBase
;
370 *(volatile int *)FEC_RBD_NEXT
= (int)fec
->rbdBase
;
373 * Enable FEC-Lite controller
375 fec
->eth
->ecntrl
|= 0x00000006;
378 if (fec
->xcv_type
!= SEVENWIRE
)
379 mpc5xxx_fec_phydump (dev
->name
);
383 * Enable SmartDMA receive task
385 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO
);
388 printf("mpc5xxx_fec_init... Done \n");
394 /********************************************************************/
395 static int mpc5xxx_fec_init_phy(struct eth_device
*dev
, bd_t
* bis
)
397 mpc5xxx_fec_priv
*fec
= (mpc5xxx_fec_priv
*)dev
->priv
;
398 const uint8 phyAddr
= CONFIG_PHY_ADDR
; /* Only one PHY */
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
405 * Initialize GPIO pins
407 if (fec
->xcv_type
== SEVENWIRE
) {
408 /* 10MBit with 7-wire operation */
409 #if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long
*)MPC5XXX_GPS_PORT_CONFIG
|= 0x00030000;
412 #else /* !CONFIG_TOTAL5200 */
414 *(vu_long
*)MPC5XXX_GPS_PORT_CONFIG
|= 0x00020000;
415 #endif /* CONFIG_TOTAL5200 */
417 /* 100MBit with MD operation */
418 *(vu_long
*)MPC5XXX_GPS_PORT_CONFIG
|= 0x00050000;
422 * Clear FEC-Lite interrupt event register(IEVENT)
424 fec
->eth
->ievent
= 0xffffffff;
427 * Set interrupt mask register
429 fec
->eth
->imask
= 0x00000000;
432 * In original Promess-provided code PHY initialization is disabled with the
433 * following comment: "Phy initialization is DISABLED for now. There was a
434 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
435 * PHY initialization for the Motion-PRO board, until a proper fix is found.
438 if (fec
->xcv_type
!= SEVENWIRE
) {
440 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
441 * and do not drop the Preamble.
443 fec
->eth
->mii_speed
= (((gd
->ipb_clk
>> 20) / 5) << 1); /* No MII for 7-wire mode */
446 if (fec
->xcv_type
!= SEVENWIRE
) {
448 * Initialize PHY(LXT971A):
450 * Generally, on power up, the LXT971A reads its configuration
451 * pins to check for forced operation, If not cofigured for
452 * forced operation, it uses auto-negotiation/parallel detection
453 * to automatically determine line operating conditions.
454 * If the PHY device on the other side of the link supports
455 * auto-negotiation, the LXT971A auto-negotiates with it
456 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
457 * support auto-negotiation, the LXT971A automatically detects
458 * the presence of either link pulses(10Mbps PHY) or Idle
459 * symbols(100Mbps) and sets its operating conditions accordingly.
461 * When auto-negotiation is controlled by software, the following
462 * steps are recommended.
465 * The physical address is dependent on hardware configuration.
472 * Reset PHY, then delay 300ns
474 miiphy_write(dev
->name
, phyAddr
, 0x0, 0x8000);
477 #if defined(CONFIG_UC101)
478 /* Set the LED configuration Register for the UC101 Board */
479 miiphy_write(dev
->name
, phyAddr
, 0x14, 0x4122);
481 if (fec
->xcv_type
== MII10
) {
483 * Force 10Base-T, FDX operation
486 printf("Forcing 10 Mbps ethernet link... ");
488 miiphy_read(dev
->name
, phyAddr
, 0x1, &phyStatus
);
490 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
492 miiphy_write(dev
->name
, phyAddr
, 0x0, 0x0180);
495 do { /* wait for link status to go down */
497 if ((timeout
--) == 0) {
499 printf("hmmm, should not have waited...");
503 miiphy_read(dev
->name
, phyAddr
, 0x1, &phyStatus
);
507 } while ((phyStatus
& 0x0004)); /* !link up */
510 do { /* wait for link status to come back up */
512 if ((timeout
--) == 0) {
513 printf("failed. Link is down.\n");
516 miiphy_read(dev
->name
, phyAddr
, 0x1, &phyStatus
);
520 } while (!(phyStatus
& 0x0004)); /* !link up */
525 } else { /* MII100 */
527 * Set the auto-negotiation advertisement register bits
529 miiphy_write(dev
->name
, phyAddr
, 0x4, 0x01e1);
532 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
534 miiphy_write(dev
->name
, phyAddr
, 0x0, 0x1200);
537 * Wait for AN completion
543 if ((timeout
--) == 0) {
545 printf("PHY auto neg 0 failed...\n");
550 if (miiphy_read(dev
->name
, phyAddr
, 0x1, &phyStatus
) != 0) {
552 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus
);
556 } while (!(phyStatus
& 0x0004));
559 printf("PHY auto neg complete! \n");
566 if (fec
->xcv_type
!= SEVENWIRE
)
567 mpc5xxx_fec_phydump (dev
->name
);
572 printf("mpc5xxx_fec_init_phy... Done \n");
578 /********************************************************************/
579 static void mpc5xxx_fec_halt(struct eth_device
*dev
)
581 #if defined(CONFIG_MPC5200)
582 struct mpc5xxx_sdma
*sdma
= (struct mpc5xxx_sdma
*)MPC5XXX_SDMA
;
584 mpc5xxx_fec_priv
*fec
= (mpc5xxx_fec_priv
*)dev
->priv
;
585 int counter
= 0xffff;
588 if (fec
->xcv_type
!= SEVENWIRE
)
589 mpc5xxx_fec_phydump (dev
->name
);
593 * mask FEC chip interrupts
598 * issue graceful stop command to the FEC transmitter if necessary
600 fec
->eth
->x_cntrl
|= 0x00000001;
603 * wait for graceful stop to register
605 while ((counter
--) && (!(fec
->eth
->ievent
& 0x10000000))) ;
608 * Disable SmartDMA tasks
610 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO
);
611 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO
);
613 #if defined(CONFIG_MPC5200)
615 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
616 * done. It doesn't work w/ the current receive task.
618 sdma
->PtdCntrl
&= ~0x00000001;
622 * Disable the Ethernet Controller
624 fec
->eth
->ecntrl
&= 0xfffffffd;
627 * Clear FIFO status registers
629 fec
->eth
->rfifo_status
&= 0x00700000;
630 fec
->eth
->tfifo_status
&= 0x00700000;
632 fec
->eth
->reset_cntrl
= 0x01000000;
635 * Issue a reset command to the FEC chip
637 fec
->eth
->ecntrl
|= 0x1;
640 * wait at least 16 clock cycles
645 printf("Ethernet task stopped\n");
650 /********************************************************************/
652 static void tfifo_print(char *devname
, mpc5xxx_fec_priv
*fec
)
654 uint16 phyAddr
= CONFIG_PHY_ADDR
;
657 if ((fec
->eth
->tfifo_lrf_ptr
!= fec
->eth
->tfifo_lwf_ptr
)
658 || (fec
->eth
->tfifo_rdptr
!= fec
->eth
->tfifo_wrptr
)) {
660 miiphy_read(devname
, phyAddr
, 0x1, &phyStatus
);
661 printf("\nphyStatus: 0x%04x\n", phyStatus
);
662 printf("ecntrl: 0x%08x\n", fec
->eth
->ecntrl
);
663 printf("ievent: 0x%08x\n", fec
->eth
->ievent
);
664 printf("x_status: 0x%08x\n", fec
->eth
->x_status
);
665 printf("tfifo: status 0x%08x\n", fec
->eth
->tfifo_status
);
667 printf(" control 0x%08x\n", fec
->eth
->tfifo_cntrl
);
668 printf(" lrfp 0x%08x\n", fec
->eth
->tfifo_lrf_ptr
);
669 printf(" lwfp 0x%08x\n", fec
->eth
->tfifo_lwf_ptr
);
670 printf(" alarm 0x%08x\n", fec
->eth
->tfifo_alarm
);
671 printf(" readptr 0x%08x\n", fec
->eth
->tfifo_rdptr
);
672 printf(" writptr 0x%08x\n", fec
->eth
->tfifo_wrptr
);
676 static void rfifo_print(char *devname
, mpc5xxx_fec_priv
*fec
)
678 uint16 phyAddr
= CONFIG_PHY_ADDR
;
681 if ((fec
->eth
->rfifo_lrf_ptr
!= fec
->eth
->rfifo_lwf_ptr
)
682 || (fec
->eth
->rfifo_rdptr
!= fec
->eth
->rfifo_wrptr
)) {
684 miiphy_read(devname
, phyAddr
, 0x1, &phyStatus
);
685 printf("\nphyStatus: 0x%04x\n", phyStatus
);
686 printf("ecntrl: 0x%08x\n", fec
->eth
->ecntrl
);
687 printf("ievent: 0x%08x\n", fec
->eth
->ievent
);
688 printf("x_status: 0x%08x\n", fec
->eth
->x_status
);
689 printf("rfifo: status 0x%08x\n", fec
->eth
->rfifo_status
);
691 printf(" control 0x%08x\n", fec
->eth
->rfifo_cntrl
);
692 printf(" lrfp 0x%08x\n", fec
->eth
->rfifo_lrf_ptr
);
693 printf(" lwfp 0x%08x\n", fec
->eth
->rfifo_lwf_ptr
);
694 printf(" alarm 0x%08x\n", fec
->eth
->rfifo_alarm
);
695 printf(" readptr 0x%08x\n", fec
->eth
->rfifo_rdptr
);
696 printf(" writptr 0x%08x\n", fec
->eth
->rfifo_wrptr
);
701 /********************************************************************/
703 static int mpc5xxx_fec_send(struct eth_device
*dev
, volatile void *eth_data
,
707 * This routine transmits one frame. This routine only accepts
708 * 6-byte Ethernet addresses.
710 mpc5xxx_fec_priv
*fec
= (mpc5xxx_fec_priv
*)dev
->priv
;
711 volatile FEC_TBD
*pTbd
;
714 printf("tbd status: 0x%04x\n", fec
->tbdBase
[0].status
);
715 tfifo_print(dev
->name
, fec
);
719 * Clear Tx BD ring at first
721 mpc5xxx_fec_tbd_scrub(fec
);
724 * Check for valid length of data.
726 if ((data_length
> 1500) || (data_length
<= 0)) {
731 * Check the number of vacant TxBDs.
733 if (fec
->cleanTbdNum
< 1) {
735 printf("No available TxBDs ...\n");
741 * Get the first TxBD to send the mac header
743 pTbd
= &fec
->tbdBase
[fec
->tbdIndex
];
744 pTbd
->dataLength
= data_length
;
745 pTbd
->dataPointer
= (uint32
)eth_data
;
746 pTbd
->status
|= FEC_TBD_LAST
| FEC_TBD_TC
| FEC_TBD_READY
;
747 fec
->tbdIndex
= (fec
->tbdIndex
+ 1) % FEC_TBD_NUM
;
750 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec
->tbdIndex
);
756 if (fec
->xcv_type
!= SEVENWIRE
) {
758 miiphy_read(dev
->name
, 0, 0x1, &phyStatus
);
762 * Enable SmartDMA transmit task
766 tfifo_print(dev
->name
, fec
);
768 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO
);
770 tfifo_print(dev
->name
, fec
);
776 fec
->cleanTbdNum
-= 1;
778 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
779 printf ("smartDMA ethernet Tx task enabled\n");
782 * wait until frame is sent .
784 while (pTbd
->status
& FEC_TBD_READY
) {
787 printf ("TDB status = %04x\n", pTbd
->status
);
795 /********************************************************************/
796 static int mpc5xxx_fec_recv(struct eth_device
*dev
)
799 * This command pulls one frame from the card
801 mpc5xxx_fec_priv
*fec
= (mpc5xxx_fec_priv
*)dev
->priv
;
802 volatile FEC_RBD
*pRbd
= &fec
->rbdBase
[fec
->rbdIndex
];
803 unsigned long ievent
;
804 int frame_length
, len
= 0;
806 uchar buff
[FEC_MAX_PKT_SIZE
];
809 printf ("mpc5xxx_fec_recv %d Start...\n", fec
->rbdIndex
);
816 * Check if any critical events have happened
818 ievent
= fec
->eth
->ievent
;
819 fec
->eth
->ievent
= ievent
;
820 if (ievent
& 0x20060000) {
821 /* BABT, Rx/Tx FIFO errors */
822 mpc5xxx_fec_halt(dev
);
823 mpc5xxx_fec_init(dev
, NULL
);
826 if (ievent
& 0x80000000) {
827 /* Heartbeat error */
828 fec
->eth
->x_cntrl
|= 0x00000001;
830 if (ievent
& 0x10000000) {
831 /* Graceful stop complete */
832 if (fec
->eth
->x_cntrl
& 0x00000001) {
833 mpc5xxx_fec_halt(dev
);
834 fec
->eth
->x_cntrl
&= ~0x00000001;
835 mpc5xxx_fec_init(dev
, NULL
);
839 if (!(pRbd
->status
& FEC_RBD_EMPTY
)) {
840 if ((pRbd
->status
& FEC_RBD_LAST
) && !(pRbd
->status
& FEC_RBD_ERR
) &&
841 ((pRbd
->dataLength
- 4) > 14)) {
844 * Get buffer address and size
846 frame
= (NBUF
*)pRbd
->dataPointer
;
847 frame_length
= pRbd
->dataLength
- 4;
852 printf("recv data hdr:");
853 for (i
= 0; i
< 14; i
++)
854 printf("%x ", *(frame
->head
+ i
));
859 * Fill the buffer and pass it to upper layers
861 memcpy(buff
, frame
->head
, 14);
862 memcpy(buff
+ 14, frame
->data
, frame_length
);
863 NetReceive(buff
, frame_length
);
867 * Reset buffer descriptor as empty
869 mpc5xxx_fec_rbd_clean(fec
, pRbd
);
871 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO
);
876 /********************************************************************/
877 int mpc5xxx_fec_initialize(bd_t
* bis
)
879 mpc5xxx_fec_priv
*fec
;
880 struct eth_device
*dev
;
882 char env_enetaddr
[6];
885 fec
= (mpc5xxx_fec_priv
*)malloc(sizeof(*fec
));
886 dev
= (struct eth_device
*)malloc(sizeof(*dev
));
887 memset(dev
, 0, sizeof *dev
);
889 fec
->eth
= (ethernet_regs
*)MPC5XXX_FEC
;
890 fec
->tbdBase
= (FEC_TBD
*)FEC_BD_BASE
;
891 fec
->rbdBase
= (FEC_RBD
*)(FEC_BD_BASE
+ FEC_TBD_NUM
* sizeof(FEC_TBD
));
892 #if defined(CONFIG_CANMB) || \
893 defined(CONFIG_CM5200) || \
894 defined(CONFIG_HMI1001) || \
895 defined(CONFIG_ICECUBE) || \
896 defined(CONFIG_INKA4X0) || \
897 defined(CONFIG_JUPITER) || \
898 defined(CONFIG_MCC200) || \
899 defined(CONFIG_MOTIONPRO) || \
900 defined(CONFIG_O2DNT) || \
901 defined(CONFIG_PM520) || \
902 defined(CONFIG_TOP5200) || \
903 defined(CONFIG_TQM5200) || \
904 defined(CONFIG_UC101) || \
905 defined(CONFIG_V38B) || \
906 defined(CONFIG_MUNICES)
907 # ifndef CONFIG_FEC_10MBIT
908 fec
->xcv_type
= MII100
;
910 fec
->xcv_type
= MII10
;
912 #elif defined(CONFIG_TOTAL5200)
913 fec
->xcv_type
= SEVENWIRE
;
915 #error fec->xcv_type not initialized.
918 dev
->priv
= (void *)fec
;
919 dev
->iobase
= MPC5XXX_FEC
;
920 dev
->init
= mpc5xxx_fec_init
;
921 dev
->halt
= mpc5xxx_fec_halt
;
922 dev
->send
= mpc5xxx_fec_send
;
923 dev
->recv
= mpc5xxx_fec_recv
;
925 sprintf(dev
->name
, "FEC ETHERNET");
928 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
929 miiphy_register (dev
->name
,
930 fec5xxx_miiphy_read
, fec5xxx_miiphy_write
);
934 * Try to set the mac address now. The fec mac address is
935 * a garbage after reset. When not using fec for booting
936 * the Linux fec driver will try to work with this garbage.
938 tmp
= getenv("ethaddr");
940 for (i
=0; i
<6; i
++) {
941 env_enetaddr
[i
] = tmp
? simple_strtoul(tmp
, &end
, 16) : 0;
943 tmp
= (*end
) ? end
+1 : end
;
945 mpc5xxx_fec_set_hwaddr(fec
, env_enetaddr
);
948 mpc5xxx_fec_init_phy(dev
, bis
);
953 /* MII-interface related functions */
954 /********************************************************************/
955 int fec5xxx_miiphy_read(char *devname
, uint8 phyAddr
, uint8 regAddr
, uint16
* retVal
)
957 ethernet_regs
*eth
= (ethernet_regs
*)MPC5XXX_FEC
;
958 uint32 reg
; /* convenient holder for the PHY register */
959 uint32 phy
; /* convenient holder for the PHY */
960 int timeout
= 0xffff;
963 * reading from any PHY's register is done by properly
964 * programming the FEC's MII data register.
966 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
967 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
969 eth
->mii_data
= (FEC_MII_DATA_ST
| FEC_MII_DATA_OP_RD
| FEC_MII_DATA_TA
| phy
| reg
);
972 * wait for the related interrupt
974 while ((timeout
--) && (!(eth
->ievent
& 0x00800000))) ;
978 printf ("Read MDIO failed...\n");
984 * clear mii interrupt bit
986 eth
->ievent
= 0x00800000;
989 * it's now safe to read the PHY's register
991 *retVal
= (uint16
) eth
->mii_data
;
996 /********************************************************************/
997 int fec5xxx_miiphy_write(char *devname
, uint8 phyAddr
, uint8 regAddr
, uint16 data
)
999 ethernet_regs
*eth
= (ethernet_regs
*)MPC5XXX_FEC
;
1000 uint32 reg
; /* convenient holder for the PHY register */
1001 uint32 phy
; /* convenient holder for the PHY */
1002 int timeout
= 0xffff;
1004 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
1005 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
1007 eth
->mii_data
= (FEC_MII_DATA_ST
| FEC_MII_DATA_OP_WR
|
1008 FEC_MII_DATA_TA
| phy
| reg
| data
);
1011 * wait for the MII interrupt
1013 while ((timeout
--) && (!(eth
->ievent
& 0x00800000))) ;
1017 printf ("Write MDIO failed...\n");
1023 * clear MII interrupt bit
1025 eth
->ievent
= 0x00800000;
1031 static uint32
local_crc32(char *string
, unsigned int crc_value
, int len
)
1035 unsigned int crc
, count
;
1041 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1045 for (i
= len
; --i
>= 0;) {
1047 for (count
= 0; count
< 8; count
++) {
1048 if ((c
& 0x01) ^ (crc
& 0x01)) {
1050 crc
= crc
^ 0xedb88320;
1059 * In big endian system, do byte swaping for crc value
1065 #endif /* CONFIG_MPC5xxx_FEC */