cpu/mpc8260/pci.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (c) 2005 MontaVista Software, Inc.
   6  * Vitaly Bordug <vbordug@ru.mvista.com>
   7  * Added support for PCI bridge on MPC8272ADS
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29
  30 #ifdef CONFIG_PCI
  31
  32 #include <pci.h>
  33 #include <mpc8260.h>
  34 #include <asm/m8260_pci.h>
  35 #include <asm/io.h>
  36 #ifdef CONFIG_OF_LIBFDT
  37 #include <libfdt.h>
  38 #include <fdt_support.h>
  39 #endif
  40
  41 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
  42 DECLARE_GLOBAL_DATA_PTR;
  43 #endif
  44
  45 /*
  46  *   Local->PCI map (from CPU)                             controlled by
  47  *   MPC826x master window
  48  *
  49  *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
  50  *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
  51  *
  52  *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
  53  *                              PCI Mem with prefetch
  54  *
  55  *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
  56  *                              PCI Mem w/o  prefetch
  57  *
  58  *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
  59  *                              32-bit PCI IO
  60  *
  61  *   PCI->Local map (from PCI)
  62  *   MPC826x slave window                                  controlled by
  63  *
  64  *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
  65  *                              MPC826x local memory
  66  */
  67
  68 /*
  69  * Slave window that allows PCI masters to access MPC826x local memory.
  70  * This window is set up using the first set of Inbound ATU registers
  71  */
  72
  73 #ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
  74 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
  75 #else
  76 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
  77 #endif
  78
  79 #ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
  80 #define PCI_SLV_MEM_BUS 0x00000000      /* PCI base */
  81 #else
  82 #define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
  83 #endif
  84
  85 #ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
  86 #define PICMR0_MASK_ATTRIB      (PICMR_MASK_512MB | PICMR_ENABLE | \
  87                                  PICMR_PREFETCH_EN)
  88 #else
  89 #define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
  90 #endif
  91
  92 /*
  93  * These are the windows that allow the CPU to access PCI address space.
  94  * All three PCI master windows, which allow the CPU to access PCI
  95  * prefetch, non prefetch, and IO space (see below), must all fit within
  96  * these windows.
  97  */
  98
  99 /* PCIBR0 */
 100 #ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
 101 #define PCI_MSTR0_LOCAL         0x80000000      /* Local base */
 102 #else
 103 #define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
 104 #endif
 105
 106 #ifndef CONFIG_SYS_PCIMSK0_MASK
 107 #define PCIMSK0_MASK            PCIMSK_1GB      /* Size of window */
 108 #else
 109 #define PCIMSK0_MASK    CONFIG_SYS_PCIMSK0_MASK
 110 #endif
 111
 112 /* PCIBR1 */
 113 #ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
 114 #define PCI_MSTR1_LOCAL         0xF4000000      /* Local base */
 115 #else
 116 #define PCI_MSTR1_LOCAL         CONFIG_SYS_PCI_MSTR1_LOCAL
 117 #endif
 118
 119 #ifndef CONFIG_SYS_PCIMSK1_MASK
 120 #define  PCIMSK1_MASK           PCIMSK_64MB     /* Size of window */
 121 #else
 122 #define  PCIMSK1_MASK           CONFIG_SYS_PCIMSK1_MASK
 123 #endif
 124
 125 /*
 126  * Master window that allows the CPU to access PCI Memory (prefetch).
 127  * This window will be setup with the first set of Outbound ATU registers
 128  * in the bridge.
 129  */
 130
 131 #ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 132 #define PCI_MSTR_MEM_LOCAL 0x80000000   /* Local base */
 133 #else
 134 #define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 135 #endif
 136
 137 #ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
 138 #define PCI_MSTR_MEM_BUS 0x80000000     /* PCI base   */
 139 #else
 140 #define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
 141 #endif
 142
 143 #ifndef CONFIG_SYS_CPU_PCI_MEM_START
 144 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
 145 #else
 146 #define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
 147 #endif
 148
 149 #ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
 150 #define PCI_MSTR_MEM_SIZE 0x10000000    /* 256MB */
 151 #else
 152 #define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
 153 #endif
 154
 155 #ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
 156 #define POCMR0_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 157 #else
 158 #define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
 159 #endif
 160
 161 /*
 162  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 163  * This window will be setup with the second set of Outbound ATU registers
 164  * in the bridge.
 165  */
 166
 167 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
 168 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
 169 #else
 170 #define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
 171 #endif
 172
 173 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
 174 #define PCI_MSTR_MEMIO_BUS 0x90000000   /* PCI base   */
 175 #else
 176 #define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
 177 #endif
 178
 179 #ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
 180 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
 181 #else
 182 #define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
 183 #endif
 184
 185 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
 186 #define PCI_MSTR_MEMIO_SIZE 0x10000000  /* 256 MB */
 187 #else
 188 #define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
 189 #endif
 190
 191 #ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
 192 #define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 193 #else
 194 #define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
 195 #endif
 196
 197 /*
 198  * Master window that allows the CPU to access PCI IO space.
 199  * This window will be setup with the third set of Outbound ATU registers
 200  * in the bridge.
 201  */
 202
 203 #ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
 204 #define PCI_MSTR_IO_LOCAL 0xA0000000    /* Local base */
 205 #else
 206 #define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
 207 #endif
 208
 209 #ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
 210 #define PCI_MSTR_IO_BUS 0xA0000000      /* PCI base   */
 211 #else
 212 #define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
 213 #endif
 214
 215 #ifndef CONFIG_SYS_CPU_PCI_IO_START
 216 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
 217 #else
 218 #define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
 219 #endif
 220
 221 #ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
 222 #define PCI_MSTR_IO_SIZE 0x10000000     /* 256MB */
 223 #else
 224 #define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
 225 #endif
 226
 227 #ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
 228 #define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
 229 #else
 230 #define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
 231 #endif
 232
 233 /* PCI bus configuration registers.
 234  */
 235
 236 #define PCI_CLASS_BRIDGE_CTLR   0x06
 237
 238
 239 static inline void pci_outl (u32 addr, u32 data)
 240 {
 241         *(volatile u32 *) addr = cpu_to_le32 (data);
 242 }
 243
 244 void pci_mpc8250_init (struct pci_controller *hose)
 245 {
 246         u16 tempShort;
 247
 248         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 249         pci_dev_t host_devno = PCI_BDF (0, 0, 0);
 250
 251         pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
 252                             CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
 253
 254         /*
 255          * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
 256          */
 257 #ifdef CONFIG_MPC8266ADS
 258         immap->im_siu_conf.sc_siumcr =
 259                 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 260                 | SIUMCR_LBPC01;
 261 #elif defined CONFIG_MPC8272
 262         immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 263                                   ~SIUMCR_BBD &
 264                                   ~SIUMCR_ESE &
 265                                   ~SIUMCR_PBSE &
 266                                   ~SIUMCR_CDIS &
 267                                   ~SIUMCR_DPPC11 &
 268                                   ~SIUMCR_L2CPC11 &
 269                                   ~SIUMCR_LBPC11 &
 270                                   ~SIUMCR_APPC11 &
 271                                   ~SIUMCR_CS10PC11 &
 272                                   ~SIUMCR_BCTLC11 &
 273                                   ~SIUMCR_MMR11)
 274                                   | SIUMCR_DPPC11
 275                                   | SIUMCR_L2CPC01
 276                                   | SIUMCR_LBPC00
 277                                   | SIUMCR_APPC10
 278                                   | SIUMCR_CS10PC00
 279                                   | SIUMCR_BCTLC00
 280                                   | SIUMCR_MMR11;
 281 #elif defined(CONFIG_TQM8272)
 282 /* nothing to do for this Board here */
 283 #else
 284         /*
 285          * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
 286          * and local bus for PCI (SIUMCR [LBPC]).
 287          */
 288         immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 289                                                 ~SIUMCR_LBPC11 &
 290                                                 ~SIUMCR_CS10PC11 &
 291                                                 ~SIUMCR_LBPC11) |
 292                                         SIUMCR_LBPC01 |
 293                                         SIUMCR_CS10PC01 |
 294                                         SIUMCR_APPC10;
 295 #endif
 296
 297         /* Make PCI lowest priority */
 298         /* Each 4 bits is a device bus request  and the MS 4bits
 299            is highest priority */
 300         /* Bus               4bit value
 301            ---               ----------
 302            CPM high          0b0000
 303            CPM middle        0b0001
 304            CPM low           0b0010
 305            PCI reguest       0b0011
 306            Reserved          0b0100
 307            Reserved          0b0101
 308            Internal Core     0b0110
 309            External Master 1 0b0111
 310            External Master 2 0b1000
 311            External Master 3 0b1001
 312            The rest are reserved */
 313         immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
 314
 315         /* Park bus on core while modifying PCI Bus accesses */
 316         immap->im_siu_conf.sc_ppc_acr = 0x6;
 317
 318         /*
 319          * Set up master windows that allow the CPU to access PCI space. These
 320          * windows are set up using the two SIU PCIBR registers.
 321          */
 322         immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
 323         immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 324
 325 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 326         immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
 327         immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
 328 #endif
 329
 330         /* Release PCI RST (by default the PCI RST signal is held low)  */
 331         immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
 332
 333         /* give it some time */
 334         {
 335 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 336                 /* Give the PCI cards more time to initialize before query
 337                    This might be good for other boards also
 338                  */
 339                 int i;
 340
 341                 for (i = 0; i < 1000; ++i)
 342 #endif
 343                         udelay (1000);
 344         }
 345
 346         /*
 347          * Set up master window that allows the CPU to access PCI Memory (prefetch)
 348          * space. This window is set up using the first set of Outbound ATU registers.
 349          */
 350         immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);        /* PCI base */
 351         immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);      /* Local base */
 352         immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);    /* Size & attribute */
 353
 354         /*
 355          * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
 356          * space. This window is set up using the second set of Outbound ATU registers.
 357          */
 358         immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);      /* PCI base */
 359         immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);    /* Local base */
 360         immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);    /* Size & attribute */
 361
 362         /*
 363          * Set up master window that allows the CPU to access PCI IO space. This window
 364          * is set up using the third set of Outbound ATU registers.
 365          */
 366         immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
 367         immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);       /* Local base */
 368         immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);    /* Size & attribute */
 369
 370         /*
 371          * Set up slave window that allows PCI masters to access MPC826x local memory.
 372          * This window is set up using the first set of Inbound ATU registers
 373          */
 374         immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);       /* PCI base */
 375         immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
 376         immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);    /* Size & attribute */
 377
 378         /* See above for description - puts PCI request as highest priority */
 379 #ifdef CONFIG_MPC8272
 380         immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
 381 #else
 382         immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
 383 #endif
 384
 385         /* Park the bus on the PCI */
 386         immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
 387
 388         /* Host mode - specify the bridge as a host-PCI bridge */
 389
 390         pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
 391                                     PCI_CLASS_BRIDGE_CTLR);
 392
 393         /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
 394         pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
 395         pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
 396                                     tempShort | PCI_COMMAND_MASTER |
 397                                     PCI_COMMAND_MEMORY);
 398
 399         /* do some bridge init, should be done on all 8260 based bridges */
 400         pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
 401                                     0x08);
 402         pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
 403                                     0xF8);
 404
 405         hose->first_busno = 0;
 406         hose->last_busno = 0xff;
 407
 408         /* System memory space */
 409 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
 410         pci_set_region (hose->regions + 0,
 411                         PCI_SLV_MEM_BUS,
 412                         PCI_SLV_MEM_LOCAL,
 413                         gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
 414 #else
 415         pci_set_region (hose->regions + 0,
 416                         CONFIG_SYS_SDRAM_BASE,
 417                         CONFIG_SYS_SDRAM_BASE,
 418                         0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
 419 #endif
 420
 421         /* PCI memory space */
 422 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 423         pci_set_region (hose->regions + 1,
 424                         PCI_MSTR_MEMIO_BUS,
 425                         PCI_MSTR_MEMIO_LOCAL,
 426                         PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
 427 #else
 428         pci_set_region (hose->regions + 1,
 429                         PCI_MSTR_MEM_BUS,
 430                         PCI_MSTR_MEM_LOCAL,
 431                         PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
 432 #endif
 433
 434         /* PCI I/O space */
 435         pci_set_region (hose->regions + 2,
 436                         PCI_MSTR_IO_BUS,
 437                         PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
 438
 439         hose->region_count = 3;
 440
 441         pci_register_hose (hose);
 442         /* Mask off master abort machine checks */
 443         immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
 444         eieio ();
 445
 446         hose->last_busno = pci_hose_scan (hose);
 447
 448
 449         /* clear the error in the error status register */
 450         immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 451
 452         /* unmask master abort machine checks */
 453         immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 454 }
 455
 456 #if defined(CONFIG_OF_LIBFDT)
 457 void ft_pci_setup(void *blob, bd_t *bd)
 458 {
 459         do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
 460                 "clock-frequency", gd->pci_clk, 1);
 461 }
 462 #endif
 463
 464 #endif /* CONFIG_PCI */