2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 DECLARE_GLOBAL_DATA_PTR
;
41 volatile immap_t
*immr
;
42 ulong clock
= gd
->cpu_clk
;
48 const struct cpu_type
{
51 } cpu_type_list
[] = {
59 CPU_TYPE_ENTRY(8347_TBGA_
),
60 CPU_TYPE_ENTRY(8347_PBGA_
),
62 CPU_TYPE_ENTRY(8358_TBGA_
),
63 CPU_TYPE_ENTRY(8358_PBGA_
),
70 immr
= (immap_t
*)CONFIG_SYS_IMMR
;
74 switch (pvr
& 0xffff0000) {
92 printf("Unknown core, ");
95 spridr
= immr
->sysconf
.spridr
;
97 for (i
= 0; i
< ARRAY_SIZE(cpu_type_list
); i
++)
98 if (cpu_type_list
[i
].partid
== PARTID_NO_E(spridr
)) {
100 puts(cpu_type_list
[i
].name
);
101 if (IS_E_PROCESSOR(spridr
))
103 if (REVID_MAJOR(spridr
) >= 2)
105 printf(", Rev: %d.%d", REVID_MAJOR(spridr
),
106 REVID_MINOR(spridr
));
110 if (i
== ARRAY_SIZE(cpu_type_list
))
111 printf("(SPRIDR %08x unknown), ", spridr
);
113 printf(" at %s MHz, ", strmhz(buf
, clock
));
115 printf("CSB: %s MHz\n", strmhz(buf
, gd
->csb_clk
));
122 * Program a UPM with the code supplied in the table.
124 * The 'dummy' variable is used to increment the MAD. 'dummy' is
125 * supposed to be a pointer to the memory of the device being
126 * programmed by the UPM. The data in the MDR is written into
127 * memory and the MAD is incremented every time there's a write
128 * to 'dummy'. Unfortunately, the current prototype for this
129 * function doesn't allow for passing the address of this
130 * device, and changing the prototype will break a number lots
131 * of other code, so we need to use a round-about way of finding
132 * the value for 'dummy'.
134 * The value can be extracted from the base address bits of the
135 * Base Register (BR) associated with the specific UPM. To find
136 * that BR, we need to scan all 8 BRs until we find the one that
137 * has its MSEL bits matching the UPM we want. Once we know the
138 * right BR, we can extract the base address bits from it.
140 * The MxMR and the BR and OR of the chosen bank should all be
141 * configured before calling this function.
144 * upm: 0=UPMA, 1=UPMB, 2=UPMC
145 * table: Pointer to an array of values to program
146 * size: Number of elements in the array. Must be 64 or less.
148 void upmconfig (uint upm
, uint
*table
, uint size
)
150 #if defined(CONFIG_MPC834X)
151 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
152 volatile lbus83xx_t
*lbus
= &immap
->lbus
;
153 volatile uchar
*dummy
= NULL
;
154 const u32 msel
= (upm
+ 4) << BR_MSEL_SHIFT
; /* What the MSEL field in BRn should be */
155 volatile u32
*mxmr
= &lbus
->mamr
+ upm
; /* Pointer to mamr, mbmr, or mcmr */
158 /* Scan all the banks to determine the base address of the device */
159 for (i
= 0; i
< 8; i
++) {
160 if ((lbus
->bank
[i
].br
& BR_MSEL
) == msel
) {
161 dummy
= (uchar
*) (lbus
->bank
[i
].br
& BR_BA
);
167 printf("Error: %s() could not find matching BR\n", __FUNCTION__
);
171 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
172 *mxmr
= (*mxmr
& 0xCFFFFFC0) | 0x10000000;
174 for (i
= 0; i
< size
; i
++) {
175 lbus
->mdr
= table
[i
];
176 __asm__
__volatile__ ("sync");
177 *dummy
= 0; /* Write the value to memory and increment MAD */
178 __asm__
__volatile__ ("sync");
179 while(((*mxmr
& 0x3f) != ((i
+ 1) & 0x3f)));
182 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
185 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__
);
192 do_reset (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
195 #ifndef MPC83xx_RESET
199 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
202 /* Interrupts and MMU off */
203 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
205 msr
&= ~( MSR_EE
| MSR_IR
| MSR_DR
);
206 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
208 /* enable Reset Control Reg */
209 immap
->reset
.rpr
= 0x52535445;
210 __asm__
__volatile__ ("sync");
211 __asm__
__volatile__ ("isync");
213 /* confirm Reset Control Reg is enabled */
214 while(!((immap
->reset
.rcer
) & RCER_CRE
));
216 printf("Resetting the board.");
221 /* perform reset, only one bit */
222 immap
->reset
.rcr
= RCR_SWHR
;
224 #else /* ! MPC83xx_RESET */
226 immap
->reset
.rmr
= RMR_CSRE
; /* Checkstop Reset enable */
228 /* Interrupts and MMU off */
229 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
231 msr
&= ~(MSR_ME
| MSR_EE
| MSR_IR
| MSR_DR
);
232 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
235 * Trying to execute the next instruction at a non-existing address
236 * should cause a machine check, resulting in reset
238 addr
= CONFIG_SYS_RESET_ADDRESS
;
240 printf("resetting the board.");
242 ((void (*)(void)) addr
) ();
243 #endif /* MPC83xx_RESET */
250 * Get timebase clock frequency (like cpu_clk in Hz)
253 unsigned long get_tbclk(void)
257 tbclk
= (gd
->bus_clk
+ 3L) / 4L;
263 #if defined(CONFIG_WATCHDOG)
264 void watchdog_reset (void)
266 int re_enable
= disable_interrupts();
268 /* Reset the 83xx watchdog */
269 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
270 immr
->wdt
.swsrr
= 0x556c;
271 immr
->wdt
.swsrr
= 0xaa39;
274 enable_interrupts ();
278 #if defined(CONFIG_DDR_ECC)
281 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
282 volatile dma83xx_t
*dma
= &immap
->dma
;
283 volatile u32 status
= swab32(dma
->dmasr0
);
284 volatile u32 dmamr0
= swab32(dma
->dmamr0
);
288 /* initialize DMASARn, DMADAR and DMAABCRn */
289 dma
->dmadar0
= (u32
)0;
290 dma
->dmasar0
= (u32
)0;
293 __asm__
__volatile__ ("sync");
294 __asm__
__volatile__ ("isync");
297 dmamr0
&= ~DMA_CHANNEL_START
;
298 dma
->dmamr0
= swab32(dmamr0
);
299 __asm__
__volatile__ ("sync");
300 __asm__
__volatile__ ("isync");
302 /* while the channel is busy, spin */
303 while(status
& DMA_CHANNEL_BUSY
) {
304 status
= swab32(dma
->dmasr0
);
307 debug("DMA-init end\n");
312 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
313 volatile dma83xx_t
*dma
= &immap
->dma
;
314 volatile u32 status
= swab32(dma
->dmasr0
);
315 volatile u32 byte_count
= swab32(dma
->dmabcr0
);
317 /* while the channel is busy, spin */
318 while (status
& DMA_CHANNEL_BUSY
) {
319 status
= swab32(dma
->dmasr0
);
322 if (status
& DMA_CHANNEL_TRANSFER_ERROR
) {
323 printf ("DMA Error: status = %x @ %d\n", status
, byte_count
);
329 int dma_xfer(void *dest
, u32 count
, void *src
)
331 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
332 volatile dma83xx_t
*dma
= &immap
->dma
;
335 /* initialize DMASARn, DMADAR and DMAABCRn */
336 dma
->dmadar0
= swab32((u32
)dest
);
337 dma
->dmasar0
= swab32((u32
)src
);
338 dma
->dmabcr0
= swab32(count
);
340 __asm__
__volatile__ ("sync");
341 __asm__
__volatile__ ("isync");
343 /* init direct transfer, clear CS bit */
344 dmamr0
= (DMA_CHANNEL_TRANSFER_MODE_DIRECT
|
345 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B
|
346 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN
);
348 dma
->dmamr0
= swab32(dmamr0
);
350 __asm__
__volatile__ ("sync");
351 __asm__
__volatile__ ("isync");
353 /* set CS to start DMA transfer */
354 dmamr0
|= DMA_CHANNEL_START
;
355 dma
->dmamr0
= swab32(dmamr0
);
356 __asm__
__volatile__ ("sync");
357 __asm__
__volatile__ ("isync");
359 return ((int)dma_check());
361 #endif /*CONFIG_DDR_ECC*/
364 * Initializes on-chip ethernet controllers.
365 * to override, implement board_eth_init()
367 int cpu_eth_init(bd_t
*bis
)
369 #if defined(CONFIG_TSEC_ENET)
370 tsec_standard_init(bis
);