cpu/mpc83xx/pci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2007
   3  *
   4  * Author: Scott Wood <scottwood@freescale.com>,
   5  * with some bits from older board-specific PCI initialization.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <pci.h>
  28
  29 #if defined(CONFIG_OF_LIBFDT)
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32 #endif
  33
  34 #include <asm/mpc8349_pci.h>
  35
  36 #ifdef CONFIG_83XX_GENERIC_PCI
  37 #define MAX_BUSES 2
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static struct pci_controller pci_hose[MAX_BUSES];
  42 static int pci_num_buses;
  43
  44 static void pci_init_bus(int bus, struct pci_region *reg)
  45 {
  46         volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
  47         volatile pot83xx_t *pot = immr->ios.pot;
  48         volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
  49         struct pci_controller *hose = &pci_hose[bus];
  50         u32 dev;
  51         u16 reg16;
  52         int i;
  53
  54         if (bus == 1)
  55                 pot += 3;
  56
  57         /* Setup outbound translation windows */
  58         for (i = 0; i < 3; i++, reg++, pot++) {
  59                 if (reg->size == 0)
  60                         break;
  61
  62                 hose->regions[i] = *reg;
  63                 hose->region_count++;
  64
  65                 pot->potar = reg->bus_start >> 12;
  66                 pot->pobar = reg->phys_start >> 12;
  67                 pot->pocmr = ~(reg->size - 1) >> 12;
  68
  69                 if (reg->flags & PCI_REGION_IO)
  70                         pot->pocmr |= POCMR_IO;
  71 #ifdef CONFIG_83XX_PCI_STREAMING
  72                 else if (reg->flags & PCI_REGION_PREFETCH)
  73                         pot->pocmr |= POCMR_SE;
  74 #endif
  75
  76                 if (bus == 1)
  77                         pot->pocmr |= POCMR_DST;
  78
  79                 pot->pocmr |= POCMR_EN;
  80         }
  81
  82         /* Point inbound translation at RAM */
  83         pci_ctrl->pitar1 = 0;
  84         pci_ctrl->pibar1 = 0;
  85         pci_ctrl->piebar1 = 0;
  86         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
  87                            PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
  88
  89         i = hose->region_count++;
  90         hose->regions[i].bus_start = 0;
  91         hose->regions[i].phys_start = 0;
  92         hose->regions[i].size = gd->ram_size;
  93         hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
  94
  95         hose->first_busno = 0;
  96         hose->last_busno = 0xff;
  97
  98         pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
  99                                  CFG_IMMR + 0x8304 + bus * 0x80);
 100
 101         pci_register_hose(hose);
 102
 103         /*
 104          * Write to Command register
 105          */
 106         reg16 = 0xff;
 107         dev = PCI_BDF(hose->first_busno, 0, 0);
 108         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
 109         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 110         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 111
 112         /*
 113          * Clear non-reserved bits in status register.
 114          */
 115         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 116         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 117         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 118
 119 #ifdef CONFIG_PCI_SCAN_SHOW
 120         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 121 #endif
 122         /*
 123          * Hose scan.
 124          */
 125         hose->last_busno = pci_hose_scan(hose);
 126 }
 127
 128 /*
 129  * The caller must have already set OCCR, and the PCI_LAW BARs
 130  * must have been set to cover all of the requested regions.
 131  *
 132  * If fewer than three regions are requested, then the region
 133  * list is terminated with a region of size 0.
 134  */
 135 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
 136 {
 137         volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
 138         int i;
 139
 140         if (num_buses > MAX_BUSES) {
 141                 printf("%d PCI buses requsted, %d supported\n",
 142                        num_buses, MAX_BUSES);
 143
 144                 num_buses = MAX_BUSES;
 145         }
 146
 147         pci_num_buses = num_buses;
 148
 149         /*
 150          * Release PCI RST Output signal.
 151          * Power on to RST high must be at least 100 ms as per PCI spec.
 152          * On warm boots only 1 ms is required.
 153          */
 154         udelay(warmboot ? 1000 : 100000);
 155
 156         for (i = 0; i < num_buses; i++)
 157                 immr->pci_ctrl[i].gcr = 1;
 158
 159         /*
 160          * RST high to first config access must be at least 2^25 cycles
 161          * as per PCI spec.  This could be cut in half if we know we're
 162          * running at 66MHz.  This could be insufficiently long if we're
 163          * running the PCI bus at significantly less than 33MHz.
 164          */
 165         udelay(1020000);
 166
 167         for (i = 0; i < num_buses; i++)
 168                 pci_init_bus(i, reg[i]);
 169 }
 170
 171 #if defined(CONFIG_OF_LIBFDT)
 172 void ft_pci_setup(void *blob, bd_t *bd)
 173 {
 174         int nodeoffset;
 175         int tmp[2];
 176         const char *path;
 177
 178         if (pci_num_buses < 1)
 179                 return;
 180
 181         nodeoffset = fdt_path_offset(blob, "/aliases");
 182         if (nodeoffset >= 0) {
 183                 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
 184                 if (path) {
 185                         tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
 186                         tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
 187                         do_fixup_by_path(blob, path, "bus-range",
 188                                 &tmp, sizeof(tmp), 1);
 189
 190                         tmp[0] = cpu_to_be32(gd->pci_clk);
 191                         do_fixup_by_path(blob, path, "clock-frequency",
 192                                 &tmp, sizeof(tmp[0]), 1);
 193                 }
 194
 195                 if (pci_num_buses < 2)
 196                         return;
 197
 198                 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
 199                 if (path) {
 200                         tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
 201                         tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
 202                         do_fixup_by_path(blob, path, "bus-range",
 203                                 &tmp, sizeof(tmp), 1);
 204
 205                         tmp[0] = cpu_to_be32(gd->pci_clk);
 206                         do_fixup_by_path(blob, path, "clock-frequency",
 207                                 &tmp, sizeof(tmp[0]), 1);
 208                 }
 209         }
 210 }
 211 #endif /* CONFIG_OF_LIBFDT */
 212 #endif /* CONFIG_83XX_GENERIC_PCI */