]>
git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/mpc83xx/pci.c
2 * Copyright (C) Freescale Semiconductor, Inc. 2007
4 * Author: Scott Wood <scottwood@freescale.com>,
5 * with some bits from older board-specific PCI initialization.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if defined(CONFIG_OF_LIBFDT)
31 #include <fdt_support.h>
34 #include <asm/mpc8349_pci.h>
38 DECLARE_GLOBAL_DATA_PTR
;
40 static struct pci_controller pci_hose
[MAX_BUSES
];
41 static int pci_num_buses
;
43 static void pci_init_bus(int bus
, struct pci_region
*reg
)
45 volatile immap_t
*immr
= (volatile immap_t
*)CONFIG_SYS_IMMR
;
46 volatile pot83xx_t
*pot
= immr
->ios
.pot
;
47 volatile pcictrl83xx_t
*pci_ctrl
= &immr
->pci_ctrl
[bus
];
48 struct pci_controller
*hose
= &pci_hose
[bus
];
56 /* Setup outbound translation windows */
57 for (i
= 0; i
< 3; i
++, reg
++, pot
++) {
61 hose
->regions
[i
] = *reg
;
64 pot
->potar
= reg
->bus_start
>> 12;
65 pot
->pobar
= reg
->phys_start
>> 12;
66 pot
->pocmr
= ~(reg
->size
- 1) >> 12;
68 if (reg
->flags
& PCI_REGION_IO
)
69 pot
->pocmr
|= POCMR_IO
;
70 #ifdef CONFIG_83XX_PCI_STREAMING
71 else if (reg
->flags
& PCI_REGION_PREFETCH
)
72 pot
->pocmr
|= POCMR_SE
;
76 pot
->pocmr
|= POCMR_DST
;
78 pot
->pocmr
|= POCMR_EN
;
81 /* Point inbound translation at RAM */
84 pci_ctrl
->piebar1
= 0;
85 pci_ctrl
->piwar1
= PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
|
86 PIWAR_WTT_SNOOP
| (__ilog2(gd
->ram_size
) - 1);
88 i
= hose
->region_count
++;
89 hose
->regions
[i
].bus_start
= 0;
90 hose
->regions
[i
].phys_start
= 0;
91 hose
->regions
[i
].size
= gd
->ram_size
;
92 hose
->regions
[i
].flags
= PCI_REGION_MEM
| PCI_REGION_MEMORY
;
94 hose
->first_busno
= 0;
95 hose
->last_busno
= 0xff;
97 pci_setup_indirect(hose
, CONFIG_SYS_IMMR
+ 0x8300 + bus
* 0x80,
98 CONFIG_SYS_IMMR
+ 0x8304 + bus
* 0x80);
100 pci_register_hose(hose
);
103 * Write to Command register
106 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
107 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
108 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
109 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
112 * Clear non-reserved bits in status register.
114 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
115 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
116 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
118 #ifdef CONFIG_PCI_SCAN_SHOW
119 printf("PCI: Bus Dev VenId DevId Class Int\n");
124 hose
->last_busno
= pci_hose_scan(hose
);
128 * The caller must have already set OCCR, and the PCI_LAW BARs
129 * must have been set to cover all of the requested regions.
131 * If fewer than three regions are requested, then the region
132 * list is terminated with a region of size 0.
134 void mpc83xx_pci_init(int num_buses
, struct pci_region
**reg
, int warmboot
)
136 volatile immap_t
*immr
= (volatile immap_t
*)CONFIG_SYS_IMMR
;
139 if (num_buses
> MAX_BUSES
) {
140 printf("%d PCI buses requsted, %d supported\n",
141 num_buses
, MAX_BUSES
);
143 num_buses
= MAX_BUSES
;
146 pci_num_buses
= num_buses
;
149 * Release PCI RST Output signal.
150 * Power on to RST high must be at least 100 ms as per PCI spec.
151 * On warm boots only 1 ms is required.
153 udelay(warmboot
? 1000 : 100000);
155 for (i
= 0; i
< num_buses
; i
++)
156 immr
->pci_ctrl
[i
].gcr
= 1;
159 * RST high to first config access must be at least 2^25 cycles
160 * as per PCI spec. This could be cut in half if we know we're
161 * running at 66MHz. This could be insufficiently long if we're
162 * running the PCI bus at significantly less than 33MHz.
166 for (i
= 0; i
< num_buses
; i
++)
167 pci_init_bus(i
, reg
[i
]);
170 #ifdef CONFIG_PCISLAVE
172 #define PCI_FUNCTION_CONFIG 0x44
173 #define PCI_FUNCTION_CFG_LOCK 0x20
176 * Unlock the configuration bit so that the host system can begin booting
178 * This should be used after you have:
179 * 1) Called mpc83xx_pci_init()
180 * 2) Set up your inbound translation windows to the appropriate size
182 void mpc83xx_pcislave_unlock(int bus
)
184 struct pci_controller
*hose
= &pci_hose
[bus
];
188 /* Unlock configuration lock in PCI function configuration register */
189 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
190 pci_hose_read_config_word (hose
, dev
, PCI_FUNCTION_CONFIG
, ®16
);
191 reg16
&= ~(PCI_FUNCTION_CFG_LOCK
);
192 pci_hose_write_config_word (hose
, dev
, PCI_FUNCTION_CONFIG
, reg16
);
196 #if defined(CONFIG_OF_LIBFDT)
197 void ft_pci_setup(void *blob
, bd_t
*bd
)
203 if (pci_num_buses
< 1)
206 nodeoffset
= fdt_path_offset(blob
, "/aliases");
207 if (nodeoffset
>= 0) {
208 path
= fdt_getprop(blob
, nodeoffset
, "pci0", NULL
);
210 tmp
[0] = cpu_to_be32(pci_hose
[0].first_busno
);
211 tmp
[1] = cpu_to_be32(pci_hose
[0].last_busno
);
212 do_fixup_by_path(blob
, path
, "bus-range",
213 &tmp
, sizeof(tmp
), 1);
215 tmp
[0] = cpu_to_be32(gd
->pci_clk
);
216 do_fixup_by_path(blob
, path
, "clock-frequency",
217 &tmp
, sizeof(tmp
[0]), 1);
220 if (pci_num_buses
< 2)
223 path
= fdt_getprop(blob
, nodeoffset
, "pci1", NULL
);
225 tmp
[0] = cpu_to_be32(pci_hose
[0].first_busno
);
226 tmp
[1] = cpu_to_be32(pci_hose
[0].last_busno
);
227 do_fixup_by_path(blob
, path
, "bus-range",
228 &tmp
, sizeof(tmp
), 1);
230 tmp
[0] = cpu_to_be32(gd
->pci_clk
);
231 do_fixup_by_path(blob
, path
, "clock-frequency",
232 &tmp
, sizeof(tmp
[0]), 1);
236 #endif /* CONFIG_OF_LIBFDT */