cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <tsec.h>
  33 #include <asm/cache.h>
  34 #include <asm/io.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 struct cpu_type cpu_type_list [] = {
  39         CPU_TYPE_ENTRY(8533, 8533),
  40         CPU_TYPE_ENTRY(8533, 8533_E),
  41         CPU_TYPE_ENTRY(8536, 8536),
  42         CPU_TYPE_ENTRY(8536, 8536_E),
  43         CPU_TYPE_ENTRY(8540, 8540),
  44         CPU_TYPE_ENTRY(8541, 8541),
  45         CPU_TYPE_ENTRY(8541, 8541_E),
  46         CPU_TYPE_ENTRY(8543, 8543),
  47         CPU_TYPE_ENTRY(8543, 8543_E),
  48         CPU_TYPE_ENTRY(8544, 8544),
  49         CPU_TYPE_ENTRY(8544, 8544_E),
  50         CPU_TYPE_ENTRY(8545, 8545),
  51         CPU_TYPE_ENTRY(8545, 8545_E),
  52         CPU_TYPE_ENTRY(8547, 8547_E),
  53         CPU_TYPE_ENTRY(8548, 8548),
  54         CPU_TYPE_ENTRY(8548, 8548_E),
  55         CPU_TYPE_ENTRY(8555, 8555),
  56         CPU_TYPE_ENTRY(8555, 8555_E),
  57         CPU_TYPE_ENTRY(8560, 8560),
  58         CPU_TYPE_ENTRY(8567, 8567),
  59         CPU_TYPE_ENTRY(8567, 8567_E),
  60         CPU_TYPE_ENTRY(8568, 8568),
  61         CPU_TYPE_ENTRY(8568, 8568_E),
  62         CPU_TYPE_ENTRY(8572, 8572),
  63         CPU_TYPE_ENTRY(8572, 8572_E),
  64 };
  65
  66 struct cpu_type *identify_cpu(u32 ver)
  67 {
  68         int i;
  69         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  70                 if (cpu_type_list[i].soc_ver == ver)
  71                         return &cpu_type_list[i];
  72
  73         return NULL;
  74 }
  75
  76 int checkcpu (void)
  77 {
  78         sys_info_t sysinfo;
  79         uint lcrr;              /* local bus clock ratio register */
  80         uint clkdiv;            /* clock divider portion of lcrr */
  81         uint pvr, svr;
  82         uint fam;
  83         uint ver;
  84         uint major, minor;
  85         struct cpu_type *cpu;
  86 #ifdef CONFIG_DDR_CLK_FREQ
  87         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  88         u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  89                 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  90 #else
  91         u32 ddr_ratio = 0;
  92 #endif
  93
  94         svr = get_svr();
  95         ver = SVR_SOC_VER(svr);
  96         major = SVR_MAJ(svr);
  97 #ifdef CONFIG_MPC8536
  98         major &= 0x7; /* the msb of this nibble is a mfg code */
  99 #endif
 100         minor = SVR_MIN(svr);
 101
 102         puts("CPU:   ");
 103
 104         cpu = identify_cpu(ver);
 105         if (cpu) {
 106                 puts(cpu->name);
 107
 108                 if (IS_E_PROCESSOR(svr))
 109                         puts("E");
 110         } else {
 111                 puts("Unknown");
 112         }
 113
 114         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 115
 116         pvr = get_pvr();
 117         fam = PVR_FAM(pvr);
 118         ver = PVR_VER(pvr);
 119         major = PVR_MAJ(pvr);
 120         minor = PVR_MIN(pvr);
 121
 122         printf("Core:  ");
 123         switch (fam) {
 124         case PVR_FAM(PVR_85xx):
 125             puts("E500");
 126             break;
 127         default:
 128             puts("Unknown");
 129             break;
 130         }
 131         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 132
 133         get_sys_info(&sysinfo);
 134
 135         puts("Clock Configuration:\n");
 136         printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
 137         printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
 138
 139         switch (ddr_ratio) {
 140         case 0x0:
 141                 printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
 142                 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 143                 break;
 144         case 0x7:
 145                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
 146                 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
 147                 break;
 148         default:
 149                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
 150                 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 151                 break;
 152         }
 153
 154 #if defined(CONFIG_SYS_LBC_LCRR)
 155         lcrr = CONFIG_SYS_LBC_LCRR;
 156 #else
 157         {
 158             volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 159
 160             lcrr = lbc->lcrr;
 161         }
 162 #endif
 163         clkdiv = lcrr & 0x0f;
 164         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 165 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
 166     defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
 167                 /*
 168                  * Yes, the entire PQ38 family use the same
 169                  * bit-representation for twice the clock divider values.
 170                  */
 171                  clkdiv *= 2;
 172 #endif
 173                 printf("LBC:%4lu MHz\n",
 174                        DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
 175         } else {
 176                 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 177         }
 178
 179 #ifdef CONFIG_CPM2
 180         printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 181 #endif
 182
 183         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 184
 185         return 0;
 186 }
 187
 188
 189 /* ------------------------------------------------------------------------- */
 190
 191 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 192 {
 193         uint pvr;
 194         uint ver;
 195         unsigned long val, msr;
 196
 197         pvr = get_pvr();
 198         ver = PVR_VER(pvr);
 199
 200         if (ver & 1){
 201         /* e500 v2 core has reset control register */
 202                 volatile unsigned int * rstcr;
 203                 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
 204                 *rstcr = 0x2;           /* HRESET_REQ */
 205                 udelay(100);
 206         }
 207
 208         /*
 209          * Fallthrough if the code above failed
 210          * Initiate hard reset in debug control register DBCR0
 211          * Make sure MSR[DE] = 1
 212          */
 213
 214         msr = mfmsr ();
 215         msr |= MSR_DE;
 216         mtmsr (msr);
 217
 218         val = mfspr(DBCR0);
 219         val |= 0x70000000;
 220         mtspr(DBCR0,val);
 221
 222         return 1;
 223 }
 224
 225
 226 /*
 227  * Get timebase clock frequency
 228  */
 229 unsigned long get_tbclk (void)
 230 {
 231         return (gd->bus_clk + 4UL)/8UL;
 232 }
 233
 234
 235 #if defined(CONFIG_WATCHDOG)
 236 void
 237 watchdog_reset(void)
 238 {
 239         int re_enable = disable_interrupts();
 240         reset_85xx_watchdog();
 241         if (re_enable) enable_interrupts();
 242 }
 243
 244 void
 245 reset_85xx_watchdog(void)
 246 {
 247         /*
 248          * Clear TSR(WIS) bit by writing 1
 249          */
 250         unsigned long val;
 251         val = mfspr(SPRN_TSR);
 252         val |= TSR_WIS;
 253         mtspr(SPRN_TSR, val);
 254 }
 255 #endif  /* CONFIG_WATCHDOG */
 256
 257 #if defined(CONFIG_DDR_ECC)
 258 void dma_init(void) {
 259         volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 260
 261         dma->satr0 = 0x02c40000;
 262         dma->datr0 = 0x02c40000;
 263         dma->sr0 = 0xfffffff; /* clear any errors */
 264         asm("sync; isync; msync");
 265         return;
 266 }
 267
 268 uint dma_check(void) {
 269         volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 270         volatile uint status = dma->sr0;
 271
 272         /* While the channel is busy, spin */
 273         while((status & 4) == 4) {
 274                 status = dma->sr0;
 275         }
 276
 277         /* clear MR0[CS] channel start bit */
 278         dma->mr0 &= 0x00000001;
 279         asm("sync;isync;msync");
 280
 281         if (status != 0) {
 282                 printf ("DMA Error: status = %x\n", status);
 283         }
 284         return status;
 285 }
 286
 287 int dma_xfer(void *dest, uint count, void *src) {
 288         volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 289
 290         dma->dar0 = (uint) dest;
 291         dma->sar0 = (uint) src;
 292         dma->bcr0 = count;
 293         dma->mr0 = 0xf000004;
 294         asm("sync;isync;msync");
 295         dma->mr0 = 0xf000005;
 296         asm("sync;isync;msync");
 297         return dma_check();
 298 }
 299 #endif
 300
 301 /*
 302  * Configures a UPM. The function requires the respective MxMR to be set
 303  * before calling this function. "size" is the number or entries, not a sizeof.
 304  */
 305 void upmconfig (uint upm, uint * table, uint size)
 306 {
 307         int i, mdr, mad, old_mad = 0;
 308         volatile u32 *mxmr;
 309         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 310         volatile u32 *brp,*orp;
 311         volatile u8* dummy = NULL;
 312         int upmmask;
 313
 314         switch (upm) {
 315         case UPMA:
 316                 mxmr = &lbc->mamr;
 317                 upmmask = BR_MS_UPMA;
 318                 break;
 319         case UPMB:
 320                 mxmr = &lbc->mbmr;
 321                 upmmask = BR_MS_UPMB;
 322                 break;
 323         case UPMC:
 324                 mxmr = &lbc->mcmr;
 325                 upmmask = BR_MS_UPMC;
 326                 break;
 327         default:
 328                 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
 329                 hang();
 330         }
 331
 332         /* Find the address for the dummy write transaction */
 333         for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
 334                  i++, brp += 2, orp += 2) {
 335
 336                 /* Look for a valid BR with selected UPM */
 337                 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
 338                         dummy = (volatile u8*)(in_be32(brp) & BR_BA);
 339                         break;
 340                 }
 341         }
 342
 343         if (i == 8) {
 344                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 345                 hang();
 346         }
 347
 348         for (i = 0; i < size; i++) {
 349                 /* 1 */
 350                 out_be32(mxmr,  (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
 351                 /* 2 */
 352                 out_be32(&lbc->mdr, table[i]);
 353                 /* 3 */
 354                 mdr = in_be32(&lbc->mdr);
 355                 /* 4 */
 356                 *(volatile u8 *)dummy = 0;
 357                 /* 5 */
 358                 do {
 359                         mad = in_be32(mxmr) & MxMR_MAD_MSK;
 360                 } while (mad <= old_mad && !(!mad && i == (size-1)));
 361                 old_mad = mad;
 362         }
 363         out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
 364 }
 365
 366
 367 /*
 368  * Initializes on-chip ethernet controllers.
 369  * to override, implement board_eth_init()
 370  */
 371 int cpu_eth_init(bd_t *bis)
 372 {
 373 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
 374         tsec_standard_init(bis);
 375 #endif
 376
 377         return 0;
 378 }