cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30 #include <command.h>
  31 #include <asm/cache.h>
  32 #include <asm/io.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 struct cpu_type cpu_type_list [] = {
  37         CPU_TYPE_ENTRY(8533, 8533),
  38         CPU_TYPE_ENTRY(8533, 8533_E),
  39         CPU_TYPE_ENTRY(8540, 8540),
  40         CPU_TYPE_ENTRY(8541, 8541),
  41         CPU_TYPE_ENTRY(8541, 8541_E),
  42         CPU_TYPE_ENTRY(8543, 8543),
  43         CPU_TYPE_ENTRY(8543, 8543_E),
  44         CPU_TYPE_ENTRY(8544, 8544),
  45         CPU_TYPE_ENTRY(8544, 8544_E),
  46         CPU_TYPE_ENTRY(8545, 8545),
  47         CPU_TYPE_ENTRY(8545, 8545_E),
  48         CPU_TYPE_ENTRY(8547, 8547_E),
  49         CPU_TYPE_ENTRY(8548, 8548),
  50         CPU_TYPE_ENTRY(8548, 8548_E),
  51         CPU_TYPE_ENTRY(8555, 8555),
  52         CPU_TYPE_ENTRY(8555, 8555_E),
  53         CPU_TYPE_ENTRY(8560, 8560),
  54         CPU_TYPE_ENTRY(8567, 8567),
  55         CPU_TYPE_ENTRY(8567, 8567_E),
  56         CPU_TYPE_ENTRY(8568, 8568),
  57         CPU_TYPE_ENTRY(8568, 8568_E),
  58         CPU_TYPE_ENTRY(8572, 8572),
  59         CPU_TYPE_ENTRY(8572, 8572_E),
  60 };
  61
  62 struct cpu_type *identify_cpu(u32 ver)
  63 {
  64         int i;
  65         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  66                 if (cpu_type_list[i].soc_ver == ver)
  67                         return &cpu_type_list[i];
  68
  69         return NULL;
  70 }
  71
  72 int checkcpu (void)
  73 {
  74         sys_info_t sysinfo;
  75         uint lcrr;              /* local bus clock ratio register */
  76         uint clkdiv;            /* clock divider portion of lcrr */
  77         uint pvr, svr;
  78         uint fam;
  79         uint ver;
  80         uint major, minor;
  81         struct cpu_type *cpu;
  82 #ifdef CONFIG_DDR_CLK_FREQ
  83         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  84         u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
  85 #else
  86         u32 ddr_ratio = 0;
  87 #endif
  88
  89         svr = get_svr();
  90         ver = SVR_SOC_VER(svr);
  91         major = SVR_MAJ(svr);
  92         minor = SVR_MIN(svr);
  93
  94         puts("CPU:   ");
  95
  96         cpu = identify_cpu(ver);
  97         if (cpu) {
  98                 puts(cpu->name);
  99
 100                 if (IS_E_PROCESSOR(svr))
 101                         puts("E");
 102         } else {
 103                 puts("Unknown");
 104         }
 105
 106         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 107
 108         pvr = get_pvr();
 109         fam = PVR_FAM(pvr);
 110         ver = PVR_VER(pvr);
 111         major = PVR_MAJ(pvr);
 112         minor = PVR_MIN(pvr);
 113
 114         printf("Core:  ");
 115         switch (fam) {
 116         case PVR_FAM(PVR_85xx):
 117             puts("E500");
 118             break;
 119         default:
 120             puts("Unknown");
 121             break;
 122         }
 123         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 124
 125         get_sys_info(&sysinfo);
 126
 127         puts("Clock Configuration:\n");
 128         printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
 129         printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
 130
 131         switch (ddr_ratio) {
 132         case 0x0:
 133                 printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
 134                 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 135                 break;
 136         case 0x7:
 137                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
 138                 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
 139                 break;
 140         default:
 141                 printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
 142                 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
 143                 break;
 144         }
 145
 146 #if defined(CFG_LBC_LCRR)
 147         lcrr = CFG_LBC_LCRR;
 148 #else
 149         {
 150             volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 151
 152             lcrr = lbc->lcrr;
 153         }
 154 #endif
 155         clkdiv = lcrr & 0x0f;
 156         if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 157 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
 158                 /*
 159                  * Yes, the entire PQ38 family use the same
 160                  * bit-representation for twice the clock divider values.
 161                  */
 162                  clkdiv *= 2;
 163 #endif
 164                 printf("LBC:%4lu MHz\n",
 165                        DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
 166         } else {
 167                 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
 168         }
 169
 170 #ifdef CONFIG_CPM2
 171         printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 172 #endif
 173
 174         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 175
 176         return 0;
 177 }
 178
 179
 180 /* ------------------------------------------------------------------------- */
 181
 182 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 183 {
 184         uint pvr;
 185         uint ver;
 186         unsigned long val, msr;
 187
 188         pvr = get_pvr();
 189         ver = PVR_VER(pvr);
 190
 191         if (ver & 1){
 192         /* e500 v2 core has reset control register */
 193                 volatile unsigned int * rstcr;
 194                 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
 195                 *rstcr = 0x2;           /* HRESET_REQ */
 196                 udelay(100);
 197         }
 198
 199         /*
 200          * Fallthrough if the code above failed
 201          * Initiate hard reset in debug control register DBCR0
 202          * Make sure MSR[DE] = 1
 203          */
 204
 205         msr = mfmsr ();
 206         msr |= MSR_DE;
 207         mtmsr (msr);
 208
 209         val = mfspr(DBCR0);
 210         val |= 0x70000000;
 211         mtspr(DBCR0,val);
 212
 213         return 1;
 214 }
 215
 216
 217 /*
 218  * Get timebase clock frequency
 219  */
 220 unsigned long get_tbclk (void)
 221 {
 222         return (gd->bus_clk + 4UL)/8UL;
 223 }
 224
 225
 226 #if defined(CONFIG_WATCHDOG)
 227 void
 228 watchdog_reset(void)
 229 {
 230         int re_enable = disable_interrupts();
 231         reset_85xx_watchdog();
 232         if (re_enable) enable_interrupts();
 233 }
 234
 235 void
 236 reset_85xx_watchdog(void)
 237 {
 238         /*
 239          * Clear TSR(WIS) bit by writing 1
 240          */
 241         unsigned long val;
 242         val = mfspr(SPRN_TSR);
 243         val |= TSR_WIS;
 244         mtspr(SPRN_TSR, val);
 245 }
 246 #endif  /* CONFIG_WATCHDOG */
 247
 248 #if defined(CONFIG_DDR_ECC)
 249 void dma_init(void) {
 250         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 251
 252         dma->satr0 = 0x02c40000;
 253         dma->datr0 = 0x02c40000;
 254         dma->sr0 = 0xfffffff; /* clear any errors */
 255         asm("sync; isync; msync");
 256         return;
 257 }
 258
 259 uint dma_check(void) {
 260         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 261         volatile uint status = dma->sr0;
 262
 263         /* While the channel is busy, spin */
 264         while((status & 4) == 4) {
 265                 status = dma->sr0;
 266         }
 267
 268         /* clear MR0[CS] channel start bit */
 269         dma->mr0 &= 0x00000001;
 270         asm("sync;isync;msync");
 271
 272         if (status != 0) {
 273                 printf ("DMA Error: status = %x\n", status);
 274         }
 275         return status;
 276 }
 277
 278 int dma_xfer(void *dest, uint count, void *src) {
 279         volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
 280
 281         dma->dar0 = (uint) dest;
 282         dma->sar0 = (uint) src;
 283         dma->bcr0 = count;
 284         dma->mr0 = 0xf000004;
 285         asm("sync;isync;msync");
 286         dma->mr0 = 0xf000005;
 287         asm("sync;isync;msync");
 288         return dma_check();
 289 }
 290 #endif
 291 /*
 292  * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
 293  * are hardcoded as "1"."size" is the number or entries, not a sizeof.
 294  */
 295 void upmconfig (uint upm, uint * table, uint size)
 296 {
 297         int i, mdr, mad, old_mad = 0;
 298         volatile u32 *mxmr;
 299         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 300         int loopval = 0x00004440;
 301         volatile u32 *brp,*orp;
 302         volatile u8* dummy = NULL;
 303         int upmmask;
 304
 305         switch (upm) {
 306         case UPMA:
 307                 mxmr = &lbc->mamr;
 308                 upmmask = BR_MS_UPMA;
 309                 break;
 310         case UPMB:
 311                 mxmr = &lbc->mbmr;
 312                 upmmask = BR_MS_UPMB;
 313                 break;
 314         case UPMC:
 315                 mxmr = &lbc->mcmr;
 316                 upmmask = BR_MS_UPMC;
 317                 break;
 318         default:
 319                 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
 320                 hang();
 321         }
 322
 323         /* Find the address for the dummy write transaction */
 324         for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
 325                  i++, brp += 2, orp += 2) {
 326
 327                 /* Look for a valid BR with selected UPM */
 328                 if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
 329                         dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
 330                         break;
 331                 }
 332         }
 333
 334         if (i == 8) {
 335                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 336                 hang();
 337         }
 338
 339         for (i = 0; i < size; i++) {
 340                 /* 1 */
 341                 out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
 342                 /* 2 */
 343                 out_be32(&lbc->mdr, table[i]);
 344                 /* 3 */
 345                 mdr = in_be32(&lbc->mdr);
 346                 /* 4 */
 347                 *(volatile u8 *)dummy = 0;
 348                 /* 5 */
 349                 do {
 350                         mad = in_be32(mxmr) & 0x3f;
 351                 } while (mad <= old_mad && !(!mad && i == (size-1)));
 352                 old_mad = mad;
 353         }
 354         out_be32(mxmr, loopval); /* OP_NORMAL */
 355 }
 356
 357 #if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
 358 /* Default initializations for TSEC controllers.  To override,
 359  * create a board-specific function called:
 360  *      int board_eth_init(bd_t *bis)
 361  */
 362
 363 extern int tsec_initialize(bd_t * bis, int index, char *devname);
 364
 365 int cpu_eth_init(bd_t *bis)
 366 {
 367 #if defined(CONFIG_TSEC1)
 368         tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
 369 #endif
 370 #if defined(CONFIG_TSEC2)
 371         tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
 372 #endif
 373 #if defined(CONFIG_MPC85XX_FEC)
 374         tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
 375 #else
 376 #if defined(CONFIG_TSEC3)
 377         tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
 378 #endif
 379 #if defined(CONFIG_TSEC4)
 380         tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
 381 #endif
 382 #endif
 383         return 0;
 384 }
 385 #endif