2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
18 unsigned int ctrl_num
)
21 volatile ccsr_ddr_t
*ddr
;
25 ddr
= (void *)CONFIG_SYS_MPC86xx_DDR_ADDR
;
28 ddr
= (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR
;
31 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__
, ctrl_num
);
35 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
37 out_be32(&ddr
->cs0_bnds
, regs
->cs
[i
].bnds
);
38 out_be32(&ddr
->cs0_config
, regs
->cs
[i
].config
);
41 out_be32(&ddr
->cs1_bnds
, regs
->cs
[i
].bnds
);
42 out_be32(&ddr
->cs1_config
, regs
->cs
[i
].config
);
45 out_be32(&ddr
->cs2_bnds
, regs
->cs
[i
].bnds
);
46 out_be32(&ddr
->cs2_config
, regs
->cs
[i
].config
);
49 out_be32(&ddr
->cs3_bnds
, regs
->cs
[i
].bnds
);
50 out_be32(&ddr
->cs3_config
, regs
->cs
[i
].config
);
54 out_be32(&ddr
->timing_cfg_3
, regs
->timing_cfg_3
);
55 out_be32(&ddr
->timing_cfg_0
, regs
->timing_cfg_0
);
56 out_be32(&ddr
->timing_cfg_1
, regs
->timing_cfg_1
);
57 out_be32(&ddr
->timing_cfg_2
, regs
->timing_cfg_2
);
58 out_be32(&ddr
->sdram_cfg_2
, regs
->ddr_sdram_cfg_2
);
59 out_be32(&ddr
->sdram_mode_1
, regs
->ddr_sdram_mode
);
60 out_be32(&ddr
->sdram_mode_2
, regs
->ddr_sdram_mode_2
);
61 out_be32(&ddr
->sdram_mode_cntl
, regs
->ddr_sdram_md_cntl
);
62 out_be32(&ddr
->sdram_interval
, regs
->ddr_sdram_interval
);
63 out_be32(&ddr
->sdram_data_init
, regs
->ddr_data_init
);
64 out_be32(&ddr
->sdram_clk_cntl
, regs
->ddr_sdram_clk_cntl
);
65 out_be32(&ddr
->init_addr
, regs
->ddr_init_addr
);
66 out_be32(&ddr
->init_ext_addr
, regs
->ddr_init_ext_addr
);
71 * 200 painful micro-seconds must elapse between
72 * the DDR clock setup and the DDR config enable.
75 asm volatile("sync;isync");
77 out_be32(&ddr
->sdram_cfg_1
, regs
->ddr_sdram_cfg
);
80 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
82 while (in_be32(&ddr
->sdram_cfg_2
) & 0x10) {
83 udelay(10000); /* throttle polling rate */