cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <command.h>
  27 #include <serial.h>
  28 #include <watchdog.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  33
  34 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  35 #define SMC_INDEX       0
  36 #define PROFF_SMC       PROFF_SMC1
  37 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  38
  39 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  40 #define SMC_INDEX       1
  41 #define PROFF_SMC       PROFF_SMC2
  42 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  43
  44 #endif /* CONFIG_8xx_CONS_SMCx */
  45
  46 #if defined(CONFIG_8xx_CONS_SCC1)       /* Console on SCC1 */
  47 #define SCC_INDEX       0
  48 #define PROFF_SCC       PROFF_SCC1
  49 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  50
  51 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  52 #define SCC_INDEX       1
  53 #define PROFF_SCC       PROFF_SCC2
  54 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  55
  56 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  57 #define SCC_INDEX       2
  58 #define PROFF_SCC       PROFF_SCC3
  59 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  60
  61 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  62 #define SCC_INDEX       3
  63 #define PROFF_SCC       PROFF_SCC4
  64 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  65
  66 #endif /* CONFIG_8xx_CONS_SCCx */
  67
  68 static void serial_setdivisor(volatile cpm8xx_t *cp)
  69 {
  70         int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  71
  72         if(divisor/16>0x1000) {
  73                 /* bad divisor, assume 50Mhz clock and 9600 baud */
  74                 divisor=(50*1000*1000 + 8*9600)/16/9600;
  75         }
  76
  77 #ifdef CFG_BRGCLK_PRESCALE
  78         divisor /= CFG_BRGCLK_PRESCALE;
  79 #endif
  80
  81         if(divisor<=0x1000) {
  82                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  83         } else {
  84                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  85         }
  86 }
  87
  88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  89
  90 /*
  91  * Minimal serial functions needed to use one of the SMC ports
  92  * as serial console interface.
  93  */
  94
  95 static void smc_setbrg (void)
  96 {
  97         volatile immap_t *im = (immap_t *)CFG_IMMR;
  98         volatile cpm8xx_t *cp = &(im->im_cpm);
  99
 100         /* Set up the baud rate generator.
 101          * See 8xx_io/commproc.c for details.
 102          *
 103          * Wire BRG1 to SMCx
 104          */
 105
 106         cp->cp_simode = 0x00000000;
 107
 108         serial_setdivisor(cp);
 109 }
 110
 111 static int smc_init (void)
 112 {
 113         volatile immap_t *im = (immap_t *)CFG_IMMR;
 114         volatile smc_t *sp;
 115         volatile smc_uart_t *up;
 116         volatile cbd_t *tbdf, *rbdf;
 117         volatile cpm8xx_t *cp = &(im->im_cpm);
 118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 119         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 120 #endif
 121         uint    dpaddr;
 122
 123         /* initialize pointers to SMC */
 124
 125         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 126         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 127
 128         /* Disable transmitter/receiver.
 129         */
 130         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 131
 132         /* Enable SDMA.
 133         */
 134         im->im_siu_conf.sc_sdcr = 1;
 135
 136         /* clear error conditions */
 137 #ifdef  CFG_SDSR
 138         im->im_sdma.sdma_sdsr = CFG_SDSR;
 139 #else
 140         im->im_sdma.sdma_sdsr = 0x83;
 141 #endif
 142
 143         /* clear SDMA interrupt mask */
 144 #ifdef  CFG_SDMR
 145         im->im_sdma.sdma_sdmr = CFG_SDMR;
 146 #else
 147         im->im_sdma.sdma_sdmr = 0x00;
 148 #endif
 149
 150 #if defined(CONFIG_8xx_CONS_SMC1)
 151         /* Use Port B for SMC1 instead of other functions.
 152         */
 153         cp->cp_pbpar |=  0x000000c0;
 154         cp->cp_pbdir &= ~0x000000c0;
 155         cp->cp_pbodr &= ~0x000000c0;
 156 #else   /* CONFIG_8xx_CONS_SMC2 */
 157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 158         /* Use Port A for SMC2 instead of other functions.
 159         */
 160         ip->iop_papar |=  0x00c0;
 161         ip->iop_padir &= ~0x00c0;
 162         ip->iop_paodr &= ~0x00c0;
 163 # else  /* must be a 860 then */
 164         /* Use Port B for SMC2 instead of other functions.
 165         */
 166         cp->cp_pbpar |=  0x00000c00;
 167         cp->cp_pbdir &= ~0x00000c00;
 168         cp->cp_pbodr &= ~0x00000c00;
 169 # endif
 170 #endif
 171
 172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
 173         /* Enable RS232 */
 174 #if defined(CONFIG_8xx_CONS_SMC1)
 175         *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
 176 #else
 177         *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
 178 #endif
 179 #endif  /* CONFIG_FADS */
 180
 181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 182         /* Enable Monitor Port Transceiver */
 183         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
 184 #endif /* CONFIG_RPXLITE */
 185
 186         /* Set the physical address of the host memory buffers in
 187          * the buffer descriptors.
 188          */
 189
 190 #ifdef CFG_ALLOC_DPRAM
 191         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 192 #else
 193         dpaddr = CPM_SERIAL_BASE ;
 194 #endif
 195
 196         /* Allocate space for two buffer descriptors in the DP ram.
 197          * For now, this address seems OK, but it may have to
 198          * change with newer versions of the firmware.
 199          * damm: allocating space after the two buffers for rx/tx data
 200          */
 201
 202         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 203         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 204         rbdf->cbd_sc = 0;
 205         tbdf = rbdf + 1;
 206         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 207         tbdf->cbd_sc = 0;
 208
 209         /* Set up the uart parameters in the parameter ram.
 210         */
 211         up->smc_rbase = dpaddr;
 212         up->smc_tbase = dpaddr+sizeof(cbd_t);
 213         up->smc_rfcr = SMC_EB;
 214         up->smc_tfcr = SMC_EB;
 215
 216 #if defined(CONFIG_MBX)
 217         board_serial_init();
 218 #endif  /* CONFIG_MBX */
 219
 220         /* Set UART mode, 8 bit, no parity, one stop.
 221          * Enable receive and transmit.
 222          */
 223         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 224
 225         /* Mask all interrupts and remove anything pending.
 226         */
 227         sp->smc_smcm = 0;
 228         sp->smc_smce = 0xff;
 229
 230         /* Set up the baud rate generator.
 231         */
 232         smc_setbrg ();
 233
 234         /* Make the first buffer the only buffer.
 235         */
 236         tbdf->cbd_sc |= BD_SC_WRAP;
 237         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 238
 239         /* Single character receive.
 240         */
 241         up->smc_mrblr = 1;
 242         up->smc_maxidl = 0;
 243
 244         /* Initialize Tx/Rx parameters.
 245         */
 246
 247         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 248           ;
 249
 250         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 251
 252         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 253           ;
 254
 255         /* Enable transmitter/receiver.
 256         */
 257         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 258
 259         return (0);
 260 }
 261
 262 static void
 263 smc_putc(const char c)
 264 {
 265         volatile cbd_t          *tbdf;
 266         volatile char           *buf;
 267         volatile smc_uart_t     *up;
 268         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 269         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 270
 271 #ifdef CONFIG_MODEM_SUPPORT
 272         if (gd->be_quiet)
 273                 return;
 274 #endif
 275
 276         if (c == '\n')
 277                 smc_putc ('\r');
 278
 279         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 280
 281         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
 282
 283         /* Wait for last character to go.
 284         */
 285
 286         buf = (char *)tbdf->cbd_bufaddr;
 287
 288         *buf = c;
 289         tbdf->cbd_datlen = 1;
 290         tbdf->cbd_sc |= BD_SC_READY;
 291         __asm__("eieio");
 292
 293         while (tbdf->cbd_sc & BD_SC_READY) {
 294                 WATCHDOG_RESET ();
 295                 __asm__("eieio");
 296         }
 297 }
 298
 299 static void
 300 smc_puts (const char *s)
 301 {
 302         while (*s) {
 303                 smc_putc (*s++);
 304         }
 305 }
 306
 307 static int
 308 smc_getc(void)
 309 {
 310         volatile cbd_t          *rbdf;
 311         volatile unsigned char  *buf;
 312         volatile smc_uart_t     *up;
 313         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 314         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 315         unsigned char           c;
 316
 317         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 318
 319         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 320
 321         /* Wait for character to show up.
 322         */
 323         buf = (unsigned char *)rbdf->cbd_bufaddr;
 324
 325         while (rbdf->cbd_sc & BD_SC_EMPTY)
 326                 WATCHDOG_RESET ();
 327
 328         c = *buf;
 329         rbdf->cbd_sc |= BD_SC_EMPTY;
 330
 331         return(c);
 332 }
 333
 334 static int
 335 smc_tstc(void)
 336 {
 337         volatile cbd_t          *rbdf;
 338         volatile smc_uart_t     *up;
 339         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 340         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 341
 342         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 343
 344         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 345
 346         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 347 }
 348
 349 struct serial_device serial_smc_device =
 350 {
 351         "serial_smc",
 352         "SMC",
 353         smc_init,
 354         smc_setbrg,
 355         smc_getc,
 356         smc_tstc,
 357         smc_putc,
 358         smc_puts,
 359 };
 360
 361 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
 362
 363 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 364     defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 365
 366 static void
 367 scc_setbrg (void)
 368 {
 369         volatile immap_t *im = (immap_t *)CFG_IMMR;
 370         volatile cpm8xx_t *cp = &(im->im_cpm);
 371
 372         /* Set up the baud rate generator.
 373          * See 8xx_io/commproc.c for details.
 374          *
 375          * Wire BRG1 to SCCx
 376          */
 377
 378         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 379
 380         serial_setdivisor(cp);
 381 }
 382
 383 static int scc_init (void)
 384 {
 385         volatile immap_t *im = (immap_t *)CFG_IMMR;
 386         volatile scc_t *sp;
 387         volatile scc_uart_t *up;
 388         volatile cbd_t *tbdf, *rbdf;
 389         volatile cpm8xx_t *cp = &(im->im_cpm);
 390         uint     dpaddr;
 391 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 392         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 393 #endif
 394
 395         /* initialize pointers to SCC */
 396
 397         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 398         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 399
 400 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
 401     {   /* Disable Ethernet, enable Serial */
 402         uchar c;
 403
 404         c = pic_read  (0x61);
 405         c &= ~0x40;     /* enable COM3 */
 406         c |=  0x80;     /* disable Ethernet */
 407         pic_write (0x61, c);
 408
 409         /* enable RTS2 */
 410         cp->cp_pbpar |=  0x2000;
 411         cp->cp_pbdat |=  0x2000;
 412         cp->cp_pbdir |=  0x2000;
 413     }
 414 #endif  /* CONFIG_LWMON */
 415
 416         /* Disable transmitter/receiver.
 417         */
 418         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 419
 420 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 421         /*
 422          * The MPC850 has SCC3 on Port B
 423          */
 424         cp->cp_pbpar |=  0x06;
 425         cp->cp_pbdir &= ~0x06;
 426         cp->cp_pbodr &= ~0x06;
 427
 428 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
 429         /*
 430          * Standard configuration for SCC's is on Part A
 431          */
 432         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 433         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 434         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 435 #else
 436         /*
 437          * The IP860 has SCC3 and SCC4 on Port D
 438          */
 439         ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 440 #endif
 441
 442         /* Allocate space for two buffer descriptors in the DP ram.
 443          */
 444
 445 #ifdef CFG_ALLOC_DPRAM
 446         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 447 #else
 448         dpaddr = CPM_SERIAL2_BASE ;
 449 #endif
 450
 451         /* Enable SDMA.
 452         */
 453         im->im_siu_conf.sc_sdcr = 0x0001;
 454
 455         /* Set the physical address of the host memory buffers in
 456          * the buffer descriptors.
 457          */
 458
 459         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 460         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 461         rbdf->cbd_sc = 0;
 462         tbdf = rbdf + 1;
 463         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 464         tbdf->cbd_sc = 0;
 465
 466         /* Set up the baud rate generator.
 467         */
 468         scc_setbrg ();
 469
 470         /* Set up the uart parameters in the parameter ram.
 471         */
 472         up->scc_genscc.scc_rbase = dpaddr;
 473         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 474
 475         /* Initialize Tx/Rx parameters.
 476         */
 477         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 478                 ;
 479         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 480
 481         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 482                 ;
 483
 484         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 485         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 486
 487         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 488         up->scc_maxidl = 0;             /* disable max idle */
 489         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 490         up->scc_parec  = 0;
 491         up->scc_frmec  = 0;
 492         up->scc_nosec  = 0;
 493         up->scc_brkec  = 0;
 494         up->scc_uaddr1 = 0;
 495         up->scc_uaddr2 = 0;
 496         up->scc_toseq  = 0;
 497         up->scc_char1  = 0x8000;
 498         up->scc_char2  = 0x8000;
 499         up->scc_char3  = 0x8000;
 500         up->scc_char4  = 0x8000;
 501         up->scc_char5  = 0x8000;
 502         up->scc_char6  = 0x8000;
 503         up->scc_char7  = 0x8000;
 504         up->scc_char8  = 0x8000;
 505         up->scc_rccm   = 0xc0ff;
 506
 507         /* Set low latency / small fifo.
 508          */
 509         sp->scc_gsmrh = SCC_GSMRH_RFW;
 510
 511         /* Set SCC(x) clock mode to 16x
 512          * See 8xx_io/commproc.c for details.
 513          *
 514          * Wire BRG1 to SCCn
 515          */
 516
 517         /* Set UART mode, clock divider 16 on Tx and Rx
 518          */
 519         sp->scc_gsmrl &= ~0xF;
 520         sp->scc_gsmrl |=
 521                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 522
 523         sp->scc_psmr  = 0;
 524         sp->scc_psmr  |= SCU_PSMR_CL;
 525
 526         /* Mask all interrupts and remove anything pending.
 527         */
 528         sp->scc_sccm = 0;
 529         sp->scc_scce = 0xffff;
 530         sp->scc_dsr  = 0x7e7e;
 531         sp->scc_psmr = 0x3000;
 532
 533         /* Make the first buffer the only buffer.
 534         */
 535         tbdf->cbd_sc |= BD_SC_WRAP;
 536         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 537
 538         /* Enable transmitter/receiver.
 539         */
 540         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 541
 542         return (0);
 543 }
 544
 545 static void
 546 scc_putc(const char c)
 547 {
 548         volatile cbd_t          *tbdf;
 549         volatile char           *buf;
 550         volatile scc_uart_t     *up;
 551         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 552         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 553
 554 #ifdef CONFIG_MODEM_SUPPORT
 555         if (gd->be_quiet)
 556                 return;
 557 #endif
 558
 559         if (c == '\n')
 560                 scc_putc ('\r');
 561
 562         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 563
 564         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 565
 566         /* Wait for last character to go.
 567         */
 568
 569         buf = (char *)tbdf->cbd_bufaddr;
 570
 571         *buf = c;
 572         tbdf->cbd_datlen = 1;
 573         tbdf->cbd_sc |= BD_SC_READY;
 574         __asm__("eieio");
 575
 576         while (tbdf->cbd_sc & BD_SC_READY) {
 577                 __asm__("eieio");
 578                 WATCHDOG_RESET ();
 579         }
 580 }
 581
 582 static void
 583 scc_puts (const char *s)
 584 {
 585         while (*s) {
 586                 scc_putc (*s++);
 587         }
 588 }
 589
 590 static int
 591 scc_getc(void)
 592 {
 593         volatile cbd_t          *rbdf;
 594         volatile unsigned char  *buf;
 595         volatile scc_uart_t     *up;
 596         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 597         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 598         unsigned char           c;
 599
 600         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 601
 602         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 603
 604         /* Wait for character to show up.
 605         */
 606         buf = (unsigned char *)rbdf->cbd_bufaddr;
 607
 608         while (rbdf->cbd_sc & BD_SC_EMPTY)
 609                 WATCHDOG_RESET ();
 610
 611         c = *buf;
 612         rbdf->cbd_sc |= BD_SC_EMPTY;
 613
 614         return(c);
 615 }
 616
 617 static int
 618 scc_tstc(void)
 619 {
 620         volatile cbd_t          *rbdf;
 621         volatile scc_uart_t     *up;
 622         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 623         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 624
 625         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 626
 627         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 628
 629         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 630 }
 631
 632 struct serial_device serial_scc_device =
 633 {
 634         "serial_scc",
 635         "SCC",
 636         scc_init,
 637         scc_setbrg,
 638         scc_getc,
 639         scc_tstc,
 640         scc_putc,
 641         scc_puts,
 642 };
 643
 644 #endif  /* CONFIG_8xx_CONS_SCCx */
 645
 646 #ifdef CONFIG_MODEM_SUPPORT
 647 void disable_putc(void)
 648 {
 649         gd->be_quiet = 1;
 650 }
 651
 652 void enable_putc(void)
 653 {
 654         gd->be_quiet = 0;
 655 }
 656 #endif
 657
 658 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 659
 660 void
 661 kgdb_serial_init(void)
 662 {
 663         int i = -1;
 664
 665         if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 666         {
 667 #if defined(CONFIG_8xx_CONS_SMC1)
 668                 i = 1;
 669 #elif defined(CONFIG_8xx_CONS_SMC2)
 670                 i = 2;
 671 #endif
 672         }
 673         else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 674         {
 675 #if defined(CONFIG_8xx_CONS_SCC1)
 676                 i = 1;
 677 #elif defined(CONFIG_8xx_CONS_SCC2)
 678                 i = 2;
 679 #elif defined(CONFIG_8xx_CONS_SCC3)
 680                 i = 3;
 681 #elif defined(CONFIG_8xx_CONS_SCC4)
 682                 i = 4;
 683 #endif
 684         }
 685
 686         if (i >= 0)
 687         {
 688                 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
 689         }
 690 }
 691
 692 void
 693 putDebugChar (int c)
 694 {
 695         serial_putc (c);
 696 }
 697
 698 void
 699 putDebugStr (const char *str)
 700 {
 701         serial_puts (str);
 702 }
 703
 704 int
 705 getDebugChar (void)
 706 {
 707         return serial_getc();
 708 }
 709
 710 void
 711 kgdb_interruptible (int yes)
 712 {
 713         return;
 714 }
 715 #endif  /* CFG_CMD_KGDB */
 716
 717 #endif  /* CONFIG_8xx_CONS_NONE */