cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <command.h>
  27 #include <serial.h>
  28 #include <watchdog.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  33
  34 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  35 #define SMC_INDEX       0
  36 #define PROFF_SMC       PROFF_SMC1
  37 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  38
  39 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  40 #define SMC_INDEX       1
  41 #define PROFF_SMC       PROFF_SMC2
  42 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  43
  44 #endif /* CONFIG_8xx_CONS_SMCx */
  45
  46 #if defined(CONFIG_8xx_CONS_SCC1)       /* Console on SCC1 */
  47 #define SCC_INDEX       0
  48 #define PROFF_SCC       PROFF_SCC1
  49 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  50
  51 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  52 #define SCC_INDEX       1
  53 #define PROFF_SCC       PROFF_SCC2
  54 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  55
  56 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  57 #define SCC_INDEX       2
  58 #define PROFF_SCC       PROFF_SCC3
  59 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  60
  61 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  62 #define SCC_INDEX       3
  63 #define PROFF_SCC       PROFF_SCC4
  64 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  65
  66 #endif /* CONFIG_8xx_CONS_SCCx */
  67
  68 static void serial_setdivisor(volatile cpm8xx_t *cp)
  69 {
  70         int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  71
  72         if(divisor/16>0x1000) {
  73                 /* bad divisor, assume 50Mhz clock and 9600 baud */
  74                 divisor=(50*1000*1000 + 8*9600)/16/9600;
  75         }
  76
  77 #ifdef CFG_BRGCLK_PRESCALE
  78         divisor /= CFG_BRGCLK_PRESCALE;
  79 #endif
  80
  81         if(divisor<=0x1000) {
  82                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  83         } else {
  84                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  85         }
  86 }
  87
  88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  89
  90 /*
  91  * Minimal serial functions needed to use one of the SMC ports
  92  * as serial console interface.
  93  */
  94
  95 static void smc_setbrg (void)
  96 {
  97         volatile immap_t *im = (immap_t *)CFG_IMMR;
  98         volatile cpm8xx_t *cp = &(im->im_cpm);
  99
 100         /* Set up the baud rate generator.
 101          * See 8xx_io/commproc.c for details.
 102          *
 103          * Wire BRG1 to SMCx
 104          */
 105
 106         cp->cp_simode = 0x00000000;
 107
 108         serial_setdivisor(cp);
 109 }
 110
 111 static int smc_init (void)
 112 {
 113         volatile immap_t *im = (immap_t *)CFG_IMMR;
 114         volatile smc_t *sp;
 115         volatile smc_uart_t *up;
 116         volatile cbd_t *tbdf, *rbdf;
 117         volatile cpm8xx_t *cp = &(im->im_cpm);
 118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 119         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 120 #endif
 121         uint    dpaddr;
 122
 123         /* initialize pointers to SMC */
 124
 125         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 126         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 127
 128         /* Disable transmitter/receiver.
 129         */
 130         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 131
 132         /* Enable SDMA.
 133         */
 134         im->im_siu_conf.sc_sdcr = 1;
 135
 136         /* clear error conditions */
 137 #ifdef  CFG_SDSR
 138         im->im_sdma.sdma_sdsr = CFG_SDSR;
 139 #else
 140         im->im_sdma.sdma_sdsr = 0x83;
 141 #endif
 142
 143         /* clear SDMA interrupt mask */
 144 #ifdef  CFG_SDMR
 145         im->im_sdma.sdma_sdmr = CFG_SDMR;
 146 #else
 147         im->im_sdma.sdma_sdmr = 0x00;
 148 #endif
 149
 150 #if defined(CONFIG_8xx_CONS_SMC1)
 151         /* Use Port B for SMC1 instead of other functions.
 152         */
 153         cp->cp_pbpar |=  0x000000c0;
 154         cp->cp_pbdir &= ~0x000000c0;
 155         cp->cp_pbodr &= ~0x000000c0;
 156 #else   /* CONFIG_8xx_CONS_SMC2 */
 157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 158         /* Use Port A for SMC2 instead of other functions.
 159         */
 160         ip->iop_papar |=  0x00c0;
 161         ip->iop_padir &= ~0x00c0;
 162         ip->iop_paodr &= ~0x00c0;
 163 # else  /* must be a 860 then */
 164         /* Use Port B for SMC2 instead of other functions.
 165         */
 166         cp->cp_pbpar |=  0x00000c00;
 167         cp->cp_pbdir &= ~0x00000c00;
 168         cp->cp_pbodr &= ~0x00000c00;
 169 # endif
 170 #endif
 171
 172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
 173         /* Enable RS232 */
 174 #if defined(CONFIG_8xx_CONS_SMC1)
 175         *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
 176 #else
 177         *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
 178 #endif
 179 #endif  /* CONFIG_FADS */
 180
 181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 182         /* Enable Monitor Port Transceiver */
 183         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
 184 #endif /* CONFIG_RPXLITE */
 185
 186         /* Set the physical address of the host memory buffers in
 187          * the buffer descriptors.
 188          */
 189
 190 #ifdef CFG_ALLOC_DPRAM
 191         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 192 #else
 193         dpaddr = CPM_SERIAL_BASE ;
 194 #endif
 195
 196         /* Allocate space for two buffer descriptors in the DP ram.
 197          * For now, this address seems OK, but it may have to
 198          * change with newer versions of the firmware.
 199          * damm: allocating space after the two buffers for rx/tx data
 200          */
 201
 202         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 203         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 204         rbdf->cbd_sc = 0;
 205         tbdf = rbdf + 1;
 206         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 207         tbdf->cbd_sc = 0;
 208
 209         /* Set up the uart parameters in the parameter ram.
 210         */
 211         up->smc_rbase = dpaddr;
 212         up->smc_tbase = dpaddr+sizeof(cbd_t);
 213         up->smc_rfcr = SMC_EB;
 214         up->smc_tfcr = SMC_EB;
 215
 216 #if defined(CONFIG_MBX)
 217         board_serial_init();
 218 #endif  /* CONFIG_MBX */
 219
 220         /* Set UART mode, 8 bit, no parity, one stop.
 221          * Enable receive and transmit.
 222          */
 223         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 224
 225         /* Mask all interrupts and remove anything pending.
 226         */
 227         sp->smc_smcm = 0;
 228         sp->smc_smce = 0xff;
 229
 230 #ifdef CFG_SPC1920_SMC1_CLK4
 231         /* clock source is PLD */
 232
 233         /* set freq to 19200 Baud */
 234         *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
 235         /* configure clk4 as input */
 236         im->im_ioport.iop_pdpar |= 0x800;
 237         im->im_ioport.iop_pddir &= ~0x800;
 238
 239         cp->cp_simode = 0x0000;
 240         cp->cp_simode |= 0x7000;
 241 #else
 242         /* Set up the baud rate generator */
 243         smc_setbrg ();
 244 #endif
 245
 246         /* Make the first buffer the only buffer.
 247         */
 248         tbdf->cbd_sc |= BD_SC_WRAP;
 249         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 250
 251         /* Single character receive.
 252         */
 253         up->smc_mrblr = 1;
 254         up->smc_maxidl = 0;
 255
 256         /* Initialize Tx/Rx parameters.
 257         */
 258
 259         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 260           ;
 261
 262         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 263
 264         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 265           ;
 266
 267         /* Enable transmitter/receiver.
 268         */
 269         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 270
 271         return (0);
 272 }
 273
 274 static void
 275 smc_putc(const char c)
 276 {
 277         volatile cbd_t          *tbdf;
 278         volatile char           *buf;
 279         volatile smc_uart_t     *up;
 280         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 281         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 282
 283 #ifdef CONFIG_MODEM_SUPPORT
 284         if (gd->be_quiet)
 285                 return;
 286 #endif
 287
 288         if (c == '\n')
 289                 smc_putc ('\r');
 290
 291         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 292
 293         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
 294
 295         /* Wait for last character to go.
 296         */
 297
 298         buf = (char *)tbdf->cbd_bufaddr;
 299
 300         *buf = c;
 301         tbdf->cbd_datlen = 1;
 302         tbdf->cbd_sc |= BD_SC_READY;
 303         __asm__("eieio");
 304
 305         while (tbdf->cbd_sc & BD_SC_READY) {
 306                 WATCHDOG_RESET ();
 307                 __asm__("eieio");
 308         }
 309 }
 310
 311 static void
 312 smc_puts (const char *s)
 313 {
 314         while (*s) {
 315                 smc_putc (*s++);
 316         }
 317 }
 318
 319 static int
 320 smc_getc(void)
 321 {
 322         volatile cbd_t          *rbdf;
 323         volatile unsigned char  *buf;
 324         volatile smc_uart_t     *up;
 325         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 326         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 327         unsigned char           c;
 328
 329         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 330
 331         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 332
 333         /* Wait for character to show up.
 334         */
 335         buf = (unsigned char *)rbdf->cbd_bufaddr;
 336
 337         while (rbdf->cbd_sc & BD_SC_EMPTY)
 338                 WATCHDOG_RESET ();
 339
 340         c = *buf;
 341         rbdf->cbd_sc |= BD_SC_EMPTY;
 342
 343         return(c);
 344 }
 345
 346 static int
 347 smc_tstc(void)
 348 {
 349         volatile cbd_t          *rbdf;
 350         volatile smc_uart_t     *up;
 351         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 352         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 353
 354         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 355
 356         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 357
 358         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 359 }
 360
 361 struct serial_device serial_smc_device =
 362 {
 363         "serial_smc",
 364         "SMC",
 365         smc_init,
 366         smc_setbrg,
 367         smc_getc,
 368         smc_tstc,
 369         smc_putc,
 370         smc_puts,
 371 };
 372
 373 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
 374
 375 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 376     defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 377
 378 static void
 379 scc_setbrg (void)
 380 {
 381         volatile immap_t *im = (immap_t *)CFG_IMMR;
 382         volatile cpm8xx_t *cp = &(im->im_cpm);
 383
 384         /* Set up the baud rate generator.
 385          * See 8xx_io/commproc.c for details.
 386          *
 387          * Wire BRG1 to SCCx
 388          */
 389
 390         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 391
 392         serial_setdivisor(cp);
 393 }
 394
 395 static int scc_init (void)
 396 {
 397         volatile immap_t *im = (immap_t *)CFG_IMMR;
 398         volatile scc_t *sp;
 399         volatile scc_uart_t *up;
 400         volatile cbd_t *tbdf, *rbdf;
 401         volatile cpm8xx_t *cp = &(im->im_cpm);
 402         uint     dpaddr;
 403 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 404         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 405 #endif
 406
 407         /* initialize pointers to SCC */
 408
 409         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 410         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 411
 412 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
 413     {   /* Disable Ethernet, enable Serial */
 414         uchar c;
 415
 416         c = pic_read  (0x61);
 417         c &= ~0x40;     /* enable COM3 */
 418         c |=  0x80;     /* disable Ethernet */
 419         pic_write (0x61, c);
 420
 421         /* enable RTS2 */
 422         cp->cp_pbpar |=  0x2000;
 423         cp->cp_pbdat |=  0x2000;
 424         cp->cp_pbdir |=  0x2000;
 425     }
 426 #endif  /* CONFIG_LWMON */
 427
 428         /* Disable transmitter/receiver.
 429         */
 430         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 431
 432 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 433         /*
 434          * The MPC850 has SCC3 on Port B
 435          */
 436         cp->cp_pbpar |=  0x06;
 437         cp->cp_pbdir &= ~0x06;
 438         cp->cp_pbodr &= ~0x06;
 439
 440 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
 441         /*
 442          * Standard configuration for SCC's is on Part A
 443          */
 444         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 445         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 446         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 447 #else
 448         /*
 449          * The IP860 has SCC3 and SCC4 on Port D
 450          */
 451         ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 452 #endif
 453
 454         /* Allocate space for two buffer descriptors in the DP ram.
 455          */
 456
 457 #ifdef CFG_ALLOC_DPRAM
 458         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 459 #else
 460         dpaddr = CPM_SERIAL2_BASE ;
 461 #endif
 462
 463         /* Enable SDMA.
 464         */
 465         im->im_siu_conf.sc_sdcr = 0x0001;
 466
 467         /* Set the physical address of the host memory buffers in
 468          * the buffer descriptors.
 469          */
 470
 471         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 472         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 473         rbdf->cbd_sc = 0;
 474         tbdf = rbdf + 1;
 475         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 476         tbdf->cbd_sc = 0;
 477
 478         /* Set up the baud rate generator.
 479         */
 480         scc_setbrg ();
 481
 482         /* Set up the uart parameters in the parameter ram.
 483         */
 484         up->scc_genscc.scc_rbase = dpaddr;
 485         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 486
 487         /* Initialize Tx/Rx parameters.
 488         */
 489         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 490                 ;
 491         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 492
 493         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 494                 ;
 495
 496         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 497         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 498
 499         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 500         up->scc_maxidl = 0;             /* disable max idle */
 501         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 502         up->scc_parec  = 0;
 503         up->scc_frmec  = 0;
 504         up->scc_nosec  = 0;
 505         up->scc_brkec  = 0;
 506         up->scc_uaddr1 = 0;
 507         up->scc_uaddr2 = 0;
 508         up->scc_toseq  = 0;
 509         up->scc_char1  = 0x8000;
 510         up->scc_char2  = 0x8000;
 511         up->scc_char3  = 0x8000;
 512         up->scc_char4  = 0x8000;
 513         up->scc_char5  = 0x8000;
 514         up->scc_char6  = 0x8000;
 515         up->scc_char7  = 0x8000;
 516         up->scc_char8  = 0x8000;
 517         up->scc_rccm   = 0xc0ff;
 518
 519         /* Set low latency / small fifo.
 520          */
 521         sp->scc_gsmrh = SCC_GSMRH_RFW;
 522
 523         /* Set SCC(x) clock mode to 16x
 524          * See 8xx_io/commproc.c for details.
 525          *
 526          * Wire BRG1 to SCCn
 527          */
 528
 529         /* Set UART mode, clock divider 16 on Tx and Rx
 530          */
 531         sp->scc_gsmrl &= ~0xF;
 532         sp->scc_gsmrl |=
 533                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 534
 535         sp->scc_psmr  = 0;
 536         sp->scc_psmr  |= SCU_PSMR_CL;
 537
 538         /* Mask all interrupts and remove anything pending.
 539         */
 540         sp->scc_sccm = 0;
 541         sp->scc_scce = 0xffff;
 542         sp->scc_dsr  = 0x7e7e;
 543         sp->scc_psmr = 0x3000;
 544
 545         /* Make the first buffer the only buffer.
 546         */
 547         tbdf->cbd_sc |= BD_SC_WRAP;
 548         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 549
 550         /* Enable transmitter/receiver.
 551         */
 552         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 553
 554         return (0);
 555 }
 556
 557 static void
 558 scc_putc(const char c)
 559 {
 560         volatile cbd_t          *tbdf;
 561         volatile char           *buf;
 562         volatile scc_uart_t     *up;
 563         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 564         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 565
 566 #ifdef CONFIG_MODEM_SUPPORT
 567         if (gd->be_quiet)
 568                 return;
 569 #endif
 570
 571         if (c == '\n')
 572                 scc_putc ('\r');
 573
 574         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 575
 576         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 577
 578         /* Wait for last character to go.
 579         */
 580
 581         buf = (char *)tbdf->cbd_bufaddr;
 582
 583         *buf = c;
 584         tbdf->cbd_datlen = 1;
 585         tbdf->cbd_sc |= BD_SC_READY;
 586         __asm__("eieio");
 587
 588         while (tbdf->cbd_sc & BD_SC_READY) {
 589                 __asm__("eieio");
 590                 WATCHDOG_RESET ();
 591         }
 592 }
 593
 594 static void
 595 scc_puts (const char *s)
 596 {
 597         while (*s) {
 598                 scc_putc (*s++);
 599         }
 600 }
 601
 602 static int
 603 scc_getc(void)
 604 {
 605         volatile cbd_t          *rbdf;
 606         volatile unsigned char  *buf;
 607         volatile scc_uart_t     *up;
 608         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 609         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 610         unsigned char           c;
 611
 612         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 613
 614         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 615
 616         /* Wait for character to show up.
 617         */
 618         buf = (unsigned char *)rbdf->cbd_bufaddr;
 619
 620         while (rbdf->cbd_sc & BD_SC_EMPTY)
 621                 WATCHDOG_RESET ();
 622
 623         c = *buf;
 624         rbdf->cbd_sc |= BD_SC_EMPTY;
 625
 626         return(c);
 627 }
 628
 629 static int
 630 scc_tstc(void)
 631 {
 632         volatile cbd_t          *rbdf;
 633         volatile scc_uart_t     *up;
 634         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 635         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 636
 637         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 638
 639         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 640
 641         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 642 }
 643
 644 struct serial_device serial_scc_device =
 645 {
 646         "serial_scc",
 647         "SCC",
 648         scc_init,
 649         scc_setbrg,
 650         scc_getc,
 651         scc_tstc,
 652         scc_putc,
 653         scc_puts,
 654 };
 655
 656 #endif  /* CONFIG_8xx_CONS_SCCx */
 657
 658 #ifdef CONFIG_MODEM_SUPPORT
 659 void disable_putc(void)
 660 {
 661         gd->be_quiet = 1;
 662 }
 663
 664 void enable_putc(void)
 665 {
 666         gd->be_quiet = 0;
 667 }
 668 #endif
 669
 670 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 671
 672 void
 673 kgdb_serial_init(void)
 674 {
 675         int i = -1;
 676
 677         if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 678         {
 679 #if defined(CONFIG_8xx_CONS_SMC1)
 680                 i = 1;
 681 #elif defined(CONFIG_8xx_CONS_SMC2)
 682                 i = 2;
 683 #endif
 684         }
 685         else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 686         {
 687 #if defined(CONFIG_8xx_CONS_SCC1)
 688                 i = 1;
 689 #elif defined(CONFIG_8xx_CONS_SCC2)
 690                 i = 2;
 691 #elif defined(CONFIG_8xx_CONS_SCC3)
 692                 i = 3;
 693 #elif defined(CONFIG_8xx_CONS_SCC4)
 694                 i = 4;
 695 #endif
 696         }
 697
 698         if (i >= 0)
 699         {
 700                 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
 701         }
 702 }
 703
 704 void
 705 putDebugChar (int c)
 706 {
 707         serial_putc (c);
 708 }
 709
 710 void
 711 putDebugStr (const char *str)
 712 {
 713         serial_puts (str);
 714 }
 715
 716 int
 717 getDebugChar (void)
 718 {
 719         return serial_getc();
 720 }
 721
 722 void
 723 kgdb_interruptible (int yes)
 724 {
 725         return;
 726 }
 727 #endif  /* CFG_CMD_KGDB */
 728
 729 #endif  /* CONFIG_8xx_CONS_NONE */