cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <command.h>
  27 #include <watchdog.h>
  28
  29 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  30
  31 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  32 #define SMC_INDEX       0
  33 #undef  SCC_INDEX
  34 #define PROFF_SMC       PROFF_SMC1
  35 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  36
  37 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  38 #define SMC_INDEX       1
  39 #undef  SCC_INDEX
  40 #define PROFF_SMC       PROFF_SMC2
  41 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  42
  43 #elif defined(CONFIG_8xx_CONS_SCC1)     /* Console on SCC1 */
  44 #undef  SMC_INDEX
  45 #define SCC_INDEX       0
  46 #define PROFF_SCC       PROFF_SCC1
  47 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  48
  49 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  50 #undef  SMC_INDEX
  51 #define SCC_INDEX       1
  52 #define PROFF_SCC       PROFF_SCC2
  53 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  54
  55 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  56 #undef  SMC_INDEX
  57 #define SCC_INDEX       2
  58 #define PROFF_SCC       PROFF_SCC3
  59 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  60
  61 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  62 #undef  SMC_INDEX
  63 #define SCC_INDEX       3
  64 #define PROFF_SCC       PROFF_SCC4
  65 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  66
  67 #else /* CONFIG_8xx_CONS_? */
  68 #error "console not correctly defined"
  69 #endif
  70
  71 static void serial_setdivisor(volatile cpm8xx_t *cp)
  72 {
  73         DECLARE_GLOBAL_DATA_PTR;
  74         int divisor=gd->cpu_clk/16/gd->baudrate;
  75
  76         if(divisor/16>0x1000) {
  77                 /* bad divisor, assume 50Mhz clock and 9600 baud */
  78                 divisor=(50*1000*1000)/16/9600;
  79         }
  80
  81 #ifdef CFG_BRGCLK_PRESCALE
  82         divisor /= CFG_BRGCLK_PRESCALE;
  83 #endif
  84
  85         if(divisor<=0x1000) {
  86                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  87         } else {
  88                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  89         }
  90 }
  91
  92 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  93
  94 /*
  95  * Minimal serial functions needed to use one of the SMC ports
  96  * as serial console interface.
  97  */
  98
  99 int serial_init (void)
 100 {
 101         volatile immap_t *im = (immap_t *)CFG_IMMR;
 102         volatile smc_t *sp;
 103         volatile smc_uart_t *up;
 104         volatile cbd_t *tbdf, *rbdf;
 105         volatile cpm8xx_t *cp = &(im->im_cpm);
 106 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 107         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 108 #endif
 109         uint    dpaddr;
 110
 111         /* initialize pointers to SMC */
 112
 113         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 114         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 115
 116         /* Disable transmitter/receiver.
 117         */
 118         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 119
 120         /* Enable SDMA.
 121         */
 122         im->im_siu_conf.sc_sdcr = 1;
 123
 124         /* clear error conditions */
 125 #ifdef  CFG_SDSR
 126         im->im_sdma.sdma_sdsr = CFG_SDSR;
 127 #else
 128         im->im_sdma.sdma_sdsr = 0x83;
 129 #endif
 130
 131         /* clear SDMA interrupt mask */
 132 #ifdef  CFG_SDMR
 133         im->im_sdma.sdma_sdmr = CFG_SDMR;
 134 #else
 135         im->im_sdma.sdma_sdmr = 0x00;
 136 #endif
 137
 138 #if defined(CONFIG_8xx_CONS_SMC1)
 139         /* Use Port B for SMC1 instead of other functions.
 140         */
 141         cp->cp_pbpar |=  0x000000c0;
 142         cp->cp_pbdir &= ~0x000000c0;
 143         cp->cp_pbodr &= ~0x000000c0;
 144 #else   /* CONFIG_8xx_CONS_SMC2 */
 145 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 146         /* Use Port A for SMC2 instead of other functions.
 147         */
 148         ip->iop_papar |=  0x00c0;
 149         ip->iop_padir &= ~0x00c0;
 150         ip->iop_paodr &= ~0x00c0;
 151 # else  /* must be a 860 then */
 152         /* Use Port B for SMC2 instead of other functions.
 153         */
 154         cp->cp_pbpar |=  0x00000c00;
 155         cp->cp_pbdir &= ~0x00000c00;
 156         cp->cp_pbodr &= ~0x00000c00;
 157 # endif
 158 #endif
 159
 160 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
 161         /* Enable RS232 */
 162 #if defined(CONFIG_8xx_CONS_SMC1)
 163         *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
 164 #else
 165         *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
 166 #endif
 167 #endif  /* CONFIG_FADS */
 168
 169 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 170         /* Enable Monitor Port Transceiver */
 171         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
 172 #endif /* CONFIG_RPXLITE */
 173
 174         /* Set the physical address of the host memory buffers in
 175          * the buffer descriptors.
 176          */
 177
 178 #ifdef CFG_ALLOC_DPRAM
 179         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 180 #else
 181         dpaddr = CPM_SERIAL_BASE ;
 182 #endif
 183
 184         /* Allocate space for two buffer descriptors in the DP ram.
 185          * For now, this address seems OK, but it may have to
 186          * change with newer versions of the firmware.
 187          * damm: allocating space after the two buffers for rx/tx data
 188          */
 189
 190         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 191         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 192         rbdf->cbd_sc = 0;
 193         tbdf = rbdf + 1;
 194         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 195         tbdf->cbd_sc = 0;
 196
 197         /* Set up the uart parameters in the parameter ram.
 198         */
 199         up->smc_rbase = dpaddr;
 200         up->smc_tbase = dpaddr+sizeof(cbd_t);
 201         up->smc_rfcr = SMC_EB;
 202         up->smc_tfcr = SMC_EB;
 203
 204 #if defined(CONFIG_MBX)
 205         board_serial_init();
 206 #endif  /* CONFIG_MBX */
 207
 208         /* Set UART mode, 8 bit, no parity, one stop.
 209          * Enable receive and transmit.
 210          */
 211         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 212
 213         /* Mask all interrupts and remove anything pending.
 214         */
 215         sp->smc_smcm = 0;
 216         sp->smc_smce = 0xff;
 217
 218         /* Set up the baud rate generator.
 219         */
 220         serial_setbrg ();
 221
 222         /* Make the first buffer the only buffer.
 223         */
 224         tbdf->cbd_sc |= BD_SC_WRAP;
 225         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 226
 227         /* Single character receive.
 228         */
 229         up->smc_mrblr = 1;
 230         up->smc_maxidl = 0;
 231
 232         /* Initialize Tx/Rx parameters.
 233         */
 234
 235         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 236           ;
 237
 238         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 239
 240         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 241           ;
 242
 243         /* Enable transmitter/receiver.
 244         */
 245         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 246
 247         return (0);
 248 }
 249
 250 void
 251 serial_setbrg (void)
 252 {
 253         volatile immap_t *im = (immap_t *)CFG_IMMR;
 254         volatile cpm8xx_t *cp = &(im->im_cpm);
 255
 256         /* Set up the baud rate generator.
 257          * See 8xx_io/commproc.c for details.
 258          *
 259          * Wire BRG1 to SMCx
 260          */
 261
 262         cp->cp_simode = 0x00000000;
 263
 264         serial_setdivisor(cp);
 265 }
 266
 267 #ifdef CONFIG_MODEM_SUPPORT
 268 void disable_putc(void)
 269 {
 270         DECLARE_GLOBAL_DATA_PTR;
 271         gd->be_quiet = 1;
 272 }
 273
 274 void enable_putc(void)
 275 {
 276         DECLARE_GLOBAL_DATA_PTR;
 277         gd->be_quiet = 0;
 278 }
 279 #endif
 280
 281 void
 282 serial_putc(const char c)
 283 {
 284         volatile cbd_t          *tbdf;
 285         volatile char           *buf;
 286         volatile smc_uart_t     *up;
 287         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 288         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 289
 290 #ifdef CONFIG_MODEM_SUPPORT
 291         DECLARE_GLOBAL_DATA_PTR;
 292
 293         if (gd->be_quiet)
 294                 return;
 295 #endif
 296
 297         if (c == '\n')
 298                 serial_putc ('\r');
 299
 300         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 301
 302         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
 303
 304         /* Wait for last character to go.
 305         */
 306
 307         buf = (char *)tbdf->cbd_bufaddr;
 308
 309         *buf = c;
 310         tbdf->cbd_datlen = 1;
 311         tbdf->cbd_sc |= BD_SC_READY;
 312         __asm__("eieio");
 313
 314         while (tbdf->cbd_sc & BD_SC_READY) {
 315                 WATCHDOG_RESET ();
 316                 __asm__("eieio");
 317         }
 318 }
 319
 320 int
 321 serial_getc(void)
 322 {
 323         volatile cbd_t          *rbdf;
 324         volatile unsigned char  *buf;
 325         volatile smc_uart_t     *up;
 326         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 327         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 328         unsigned char           c;
 329
 330         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 331
 332         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 333
 334         /* Wait for character to show up.
 335         */
 336         buf = (unsigned char *)rbdf->cbd_bufaddr;
 337
 338         while (rbdf->cbd_sc & BD_SC_EMPTY)
 339                 WATCHDOG_RESET ();
 340
 341         c = *buf;
 342         rbdf->cbd_sc |= BD_SC_EMPTY;
 343
 344         return(c);
 345 }
 346
 347 int
 348 serial_tstc()
 349 {
 350         volatile cbd_t          *rbdf;
 351         volatile smc_uart_t     *up;
 352         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 353         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 354
 355         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 356
 357         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 358
 359         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 360 }
 361
 362 #else   /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
 363
 364 int serial_init (void)
 365 {
 366         volatile immap_t *im = (immap_t *)CFG_IMMR;
 367         volatile scc_t *sp;
 368         volatile scc_uart_t *up;
 369         volatile cbd_t *tbdf, *rbdf;
 370         volatile cpm8xx_t *cp = &(im->im_cpm);
 371         uint     dpaddr;
 372 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 373         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 374 #endif
 375
 376         /* initialize pointers to SCC */
 377
 378         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 379         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 380
 381 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
 382     {   /* Disable Ethernet, enable Serial */
 383         uchar c;
 384
 385         c = pic_read  (0x61);
 386         c &= ~0x40;     /* enable COM3 */
 387         c |=  0x80;     /* disable Ethernet */
 388         pic_write (0x61, c);
 389
 390         /* enable RTS2 */
 391         cp->cp_pbpar |=  0x2000;
 392         cp->cp_pbdat |=  0x2000;
 393         cp->cp_pbdir |=  0x2000;
 394     }
 395 #endif  /* CONFIG_LWMON */
 396
 397         /* Disable transmitter/receiver.
 398         */
 399         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 400
 401 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 402         /*
 403          * The MPC850 has SCC3 on Port B
 404          */
 405         cp->cp_pbpar |=  0x06;
 406         cp->cp_pbdir &= ~0x06;
 407         cp->cp_pbodr &= ~0x06;
 408
 409 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
 410         /*
 411          * Standard configuration for SCC's is on Part A
 412          */
 413         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 414         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 415         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 416 #else
 417         /*
 418          * The IP860 has SCC3 and SCC4 on Port D
 419          */
 420         ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 421 #endif
 422
 423         /* Allocate space for two buffer descriptors in the DP ram.
 424          */
 425
 426 #ifdef CFG_ALLOC_DPRAM
 427         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 428 #else
 429         dpaddr = CPM_SERIAL_BASE ;
 430 #endif
 431
 432         /* Enable SDMA.
 433         */
 434         im->im_siu_conf.sc_sdcr = 0x0001;
 435
 436         /* Set the physical address of the host memory buffers in
 437          * the buffer descriptors.
 438          */
 439
 440         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 441         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 442         rbdf->cbd_sc = 0;
 443         tbdf = rbdf + 1;
 444         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 445         tbdf->cbd_sc = 0;
 446
 447         /* Set up the baud rate generator.
 448         */
 449         serial_setbrg ();
 450
 451         /* Set up the uart parameters in the parameter ram.
 452         */
 453         up->scc_genscc.scc_rbase = dpaddr;
 454         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 455
 456         /* Initialize Tx/Rx parameters.
 457         */
 458         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 459                 ;
 460         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 461
 462         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 463                 ;
 464
 465         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 466         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 467
 468         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 469         up->scc_maxidl = 0;             /* disable max idle */
 470         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 471         up->scc_parec  = 0;
 472         up->scc_frmec  = 0;
 473         up->scc_nosec  = 0;
 474         up->scc_brkec  = 0;
 475         up->scc_uaddr1 = 0;
 476         up->scc_uaddr2 = 0;
 477         up->scc_toseq  = 0;
 478         up->scc_char1  = 0x8000;
 479         up->scc_char2  = 0x8000;
 480         up->scc_char3  = 0x8000;
 481         up->scc_char4  = 0x8000;
 482         up->scc_char5  = 0x8000;
 483         up->scc_char6  = 0x8000;
 484         up->scc_char7  = 0x8000;
 485         up->scc_char8  = 0x8000;
 486         up->scc_rccm   = 0xc0ff;
 487
 488         /* Set low latency / small fifo.
 489          */
 490         sp->scc_gsmrh = SCC_GSMRH_RFW;
 491
 492         /* Set SCC(x) clock mode to 16x
 493          * See 8xx_io/commproc.c for details.
 494          *
 495          * Wire BRG1 to SCCn
 496          */
 497
 498         /* Set UART mode, clock divider 16 on Tx and Rx
 499          */
 500         sp->scc_gsmrl |=
 501                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 502
 503         sp->scc_psmr  |= SCU_PSMR_CL;
 504
 505         /* Mask all interrupts and remove anything pending.
 506         */
 507         sp->scc_sccm = 0;
 508         sp->scc_scce = 0xffff;
 509         sp->scc_dsr  = 0x7e7e;
 510         sp->scc_psmr = 0x3000;
 511
 512         /* Make the first buffer the only buffer.
 513         */
 514         tbdf->cbd_sc |= BD_SC_WRAP;
 515         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 516
 517         /* Enable transmitter/receiver.
 518         */
 519         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 520
 521         return (0);
 522 }
 523
 524 void
 525 serial_setbrg (void)
 526 {
 527         volatile immap_t *im = (immap_t *)CFG_IMMR;
 528         volatile cpm8xx_t *cp = &(im->im_cpm);
 529
 530         /* Set up the baud rate generator.
 531          * See 8xx_io/commproc.c for details.
 532          *
 533          * Wire BRG1 to SCCx
 534          */
 535
 536         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 537
 538         serial_setdivisor(cp);
 539 }
 540
 541 void
 542 serial_putc(const char c)
 543 {
 544         volatile cbd_t          *tbdf;
 545         volatile char           *buf;
 546         volatile scc_uart_t     *up;
 547         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 548         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 549
 550         if (c == '\n')
 551                 serial_putc ('\r');
 552
 553         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 554
 555         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 556
 557         /* Wait for last character to go.
 558         */
 559
 560         buf = (char *)tbdf->cbd_bufaddr;
 561
 562         *buf = c;
 563         tbdf->cbd_datlen = 1;
 564         tbdf->cbd_sc |= BD_SC_READY;
 565         __asm__("eieio");
 566
 567         while (tbdf->cbd_sc & BD_SC_READY) {
 568                 __asm__("eieio");
 569                 WATCHDOG_RESET ();
 570         }
 571 }
 572
 573 int
 574 serial_getc(void)
 575 {
 576         volatile cbd_t          *rbdf;
 577         volatile unsigned char  *buf;
 578         volatile scc_uart_t     *up;
 579         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 580         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 581         unsigned char           c;
 582
 583         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 584
 585         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 586
 587         /* Wait for character to show up.
 588         */
 589         buf = (unsigned char *)rbdf->cbd_bufaddr;
 590
 591         while (rbdf->cbd_sc & BD_SC_EMPTY)
 592                 WATCHDOG_RESET ();
 593
 594         c = *buf;
 595         rbdf->cbd_sc |= BD_SC_EMPTY;
 596
 597         return(c);
 598 }
 599
 600 int
 601 serial_tstc()
 602 {
 603         volatile cbd_t          *rbdf;
 604         volatile scc_uart_t     *up;
 605         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 606         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 607
 608         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 609
 610         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 611
 612         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 613 }
 614
 615 #endif  /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
 616
 617
 618 void
 619 serial_puts (const char *s)
 620 {
 621         while (*s) {
 622                 serial_putc (*s++);
 623         }
 624 }
 625
 626
 627 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 628
 629 void
 630 kgdb_serial_init(void)
 631 {
 632 #if defined(CONFIG_8xx_CONS_SMC1)
 633         serial_printf("[on SMC1] ");
 634 #elif defined(CONFIG_8xx_CONS_SMC2)
 635         serial_printf("[on SMC2] ");
 636 #elif defined(CONFIG_8xx_CONS_SCC1)
 637         serial_printf("[on SCC1] ");
 638 #elif defined(CONFIG_8xx_CONS_SCC2)
 639         serial_printf("[on SCC2] ");
 640 #elif defined(CONFIG_8xx_CONS_SCC3)
 641         serial_printf("[on SCC3] ");
 642 #elif defined(CONFIG_8xx_CONS_SCC4)
 643         serial_printf("[on SCC4] ");
 644 #endif
 645 }
 646
 647 void
 648 putDebugChar (int c)
 649 {
 650         serial_putc (c);
 651 }
 652
 653 void
 654 putDebugStr (const char *str)
 655 {
 656         serial_puts (str);
 657 }
 658
 659 int
 660 getDebugChar (void)
 661 {
 662         return serial_getc();
 663 }
 664
 665 void
 666 kgdb_interruptible (int yes)
 667 {
 668         return;
 669 }
 670 #endif  /* CFG_CMD_KGDB */
 671
 672 #endif  /* CONFIG_8xx_CONS_NONE */