3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 DECLARE_GLOBAL_DATA_PTR
;
32 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
34 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
36 #define PROFF_SMC PROFF_SMC1
37 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
39 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
41 #define PROFF_SMC PROFF_SMC2
42 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
44 #endif /* CONFIG_8xx_CONS_SMCx */
46 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
48 #define PROFF_SCC PROFF_SCC1
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
51 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
53 #define PROFF_SCC PROFF_SCC2
54 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
56 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
63 #define PROFF_SCC PROFF_SCC4
64 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
66 #endif /* CONFIG_8xx_CONS_SCCx */
68 static void serial_setdivisor(volatile cpm8xx_t
*cp
)
70 int divisor
=(gd
->cpu_clk
+ 8*gd
->baudrate
)/16/gd
->baudrate
;
72 if(divisor
/16>0x1000) {
73 /* bad divisor, assume 50Mhz clock and 9600 baud */
74 divisor
=(50*1000*1000 + 8*9600)/16/9600;
77 #ifdef CFG_BRGCLK_PRESCALE
78 divisor
/= CFG_BRGCLK_PRESCALE
;
82 cp
->cp_brgc1
=((divisor
-1)<<1) | CPM_BRG_EN
;
84 cp
->cp_brgc1
=((divisor
/16-1)<<1) | CPM_BRG_EN
| CPM_BRG_DIV16
;
88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
95 static void smc_setbrg (void)
97 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
98 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
100 /* Set up the baud rate generator.
101 * See 8xx_io/commproc.c for details.
106 cp
->cp_simode
= 0x00000000;
108 serial_setdivisor(cp
);
111 static int smc_init (void)
113 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
115 volatile smc_uart_t
*up
;
116 volatile cbd_t
*tbdf
, *rbdf
;
117 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
119 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
123 /* initialize pointers to SMC */
125 sp
= (smc_t
*) &(cp
->cp_smc
[SMC_INDEX
]);
126 up
= (smc_uart_t
*) &cp
->cp_dparam
[PROFF_SMC
];
128 /* Disable transmitter/receiver.
130 sp
->smc_smcmr
&= ~(SMCMR_REN
| SMCMR_TEN
);
134 im
->im_siu_conf
.sc_sdcr
= 1;
136 /* clear error conditions */
138 im
->im_sdma
.sdma_sdsr
= CFG_SDSR
;
140 im
->im_sdma
.sdma_sdsr
= 0x83;
143 /* clear SDMA interrupt mask */
145 im
->im_sdma
.sdma_sdmr
= CFG_SDMR
;
147 im
->im_sdma
.sdma_sdmr
= 0x00;
150 #if defined(CONFIG_8xx_CONS_SMC1)
151 /* Use Port B for SMC1 instead of other functions.
153 cp
->cp_pbpar
|= 0x000000c0;
154 cp
->cp_pbdir
&= ~0x000000c0;
155 cp
->cp_pbodr
&= ~0x000000c0;
156 #else /* CONFIG_8xx_CONS_SMC2 */
157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
158 /* Use Port A for SMC2 instead of other functions.
160 ip
->iop_papar
|= 0x00c0;
161 ip
->iop_padir
&= ~0x00c0;
162 ip
->iop_paodr
&= ~0x00c0;
163 # else /* must be a 860 then */
164 /* Use Port B for SMC2 instead of other functions.
166 cp
->cp_pbpar
|= 0x00000c00;
167 cp
->cp_pbdir
&= ~0x00000c00;
168 cp
->cp_pbodr
&= ~0x00000c00;
172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
174 #if defined(CONFIG_8xx_CONS_SMC1)
175 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_1
;
177 *((uint
*) BCSR1
) &= ~BCSR1_RS232EN_2
;
179 #endif /* CONFIG_FADS */
181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
182 /* Enable Monitor Port Transceiver */
183 *((uchar
*) BCSR0
) |= BCSR0_ENMONXCVR
;
184 #endif /* CONFIG_RPXLITE */
186 /* Set the physical address of the host memory buffers in
187 * the buffer descriptors.
190 #ifdef CFG_ALLOC_DPRAM
191 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
193 dpaddr
= CPM_SERIAL_BASE
;
196 /* Allocate space for two buffer descriptors in the DP ram.
197 * For now, this address seems OK, but it may have to
198 * change with newer versions of the firmware.
199 * damm: allocating space after the two buffers for rx/tx data
202 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
203 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
206 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
209 /* Set up the uart parameters in the parameter ram.
211 up
->smc_rbase
= dpaddr
;
212 up
->smc_tbase
= dpaddr
+sizeof(cbd_t
);
213 up
->smc_rfcr
= SMC_EB
;
214 up
->smc_tfcr
= SMC_EB
;
216 #if defined(CONFIG_MBX)
218 #endif /* CONFIG_MBX */
220 /* Set UART mode, 8 bit, no parity, one stop.
221 * Enable receive and transmit.
223 sp
->smc_smcmr
= smcr_mk_clen(9) | SMCMR_SM_UART
;
225 /* Mask all interrupts and remove anything pending.
230 #ifdef CFG_SPC1920_SMC1_CLK4
231 /* clock source is PLD */
233 /* set freq to 19200 Baud */
234 *((volatile uchar
*) CFG_SPC1920_PLD_BASE
+6) = 0x3;
235 /* configure clk4 as input */
236 im
->im_ioport
.iop_pdpar
|= 0x800;
237 im
->im_ioport
.iop_pddir
&= ~0x800;
239 cp
->cp_simode
= ((cp
->cp_simode
& ~0xf000) | 0x7000);
241 /* Set up the baud rate generator */
245 /* Make the first buffer the only buffer.
247 tbdf
->cbd_sc
|= BD_SC_WRAP
;
248 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
250 /* Single character receive.
255 /* Initialize Tx/Rx parameters.
258 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
261 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SMC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
263 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
266 /* Enable transmitter/receiver.
268 sp
->smc_smcmr
|= SMCMR_REN
| SMCMR_TEN
;
274 smc_putc(const char c
)
276 volatile cbd_t
*tbdf
;
278 volatile smc_uart_t
*up
;
279 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
280 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
282 #ifdef CONFIG_MODEM_SUPPORT
290 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
292 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_tbase
];
294 /* Wait for last character to go.
297 buf
= (char *)tbdf
->cbd_bufaddr
;
300 tbdf
->cbd_datlen
= 1;
301 tbdf
->cbd_sc
|= BD_SC_READY
;
304 while (tbdf
->cbd_sc
& BD_SC_READY
) {
311 smc_puts (const char *s
)
321 volatile cbd_t
*rbdf
;
322 volatile unsigned char *buf
;
323 volatile smc_uart_t
*up
;
324 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
325 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
328 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
330 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
332 /* Wait for character to show up.
334 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
336 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
340 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
348 volatile cbd_t
*rbdf
;
349 volatile smc_uart_t
*up
;
350 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
351 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
353 up
= (smc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SMC
];
355 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->smc_rbase
];
357 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
360 struct serial_device serial_smc_device
=
372 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
374 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
375 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
380 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
381 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
383 /* Set up the baud rate generator.
384 * See 8xx_io/commproc.c for details.
389 cp
->cp_sicr
&= ~(0x000000FF << (8 * SCC_INDEX
));
391 serial_setdivisor(cp
);
394 static int scc_init (void)
396 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
398 volatile scc_uart_t
*up
;
399 volatile cbd_t
*tbdf
, *rbdf
;
400 volatile cpm8xx_t
*cp
= &(im
->im_cpm
);
402 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
403 volatile iop8xx_t
*ip
= (iop8xx_t
*)&(im
->im_ioport
);
406 /* initialize pointers to SCC */
408 sp
= (scc_t
*) &(cp
->cp_scc
[SCC_INDEX
]);
409 up
= (scc_uart_t
*) &cp
->cp_dparam
[PROFF_SCC
];
411 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
412 { /* Disable Ethernet, enable Serial */
416 c
&= ~0x40; /* enable COM3 */
417 c
|= 0x80; /* disable Ethernet */
421 cp
->cp_pbpar
|= 0x2000;
422 cp
->cp_pbdat
|= 0x2000;
423 cp
->cp_pbdir
|= 0x2000;
425 #endif /* CONFIG_LWMON */
427 /* Disable transmitter/receiver.
429 sp
->scc_gsmrl
&= ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
431 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
433 * The MPC850 has SCC3 on Port B
435 cp
->cp_pbpar
|= 0x06;
436 cp
->cp_pbdir
&= ~0x06;
437 cp
->cp_pbodr
&= ~0x06;
439 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
441 * Standard configuration for SCC's is on Part A
443 ip
->iop_papar
|= ((3 << (2 * SCC_INDEX
)));
444 ip
->iop_padir
&= ~((3 << (2 * SCC_INDEX
)));
445 ip
->iop_paodr
&= ~((3 << (2 * SCC_INDEX
)));
448 * The IP860 has SCC3 and SCC4 on Port D
450 ip
->iop_pdpar
|= ((3 << (2 * SCC_INDEX
)));
453 /* Allocate space for two buffer descriptors in the DP ram.
456 #ifdef CFG_ALLOC_DPRAM
457 dpaddr
= dpram_alloc_align (sizeof(cbd_t
)*2 + 2, 8) ;
459 dpaddr
= CPM_SERIAL2_BASE
;
464 im
->im_siu_conf
.sc_sdcr
= 0x0001;
466 /* Set the physical address of the host memory buffers in
467 * the buffer descriptors.
470 rbdf
= (cbd_t
*)&cp
->cp_dpmem
[dpaddr
];
471 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
474 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
477 /* Set up the baud rate generator.
481 /* Set up the uart parameters in the parameter ram.
483 up
->scc_genscc
.scc_rbase
= dpaddr
;
484 up
->scc_genscc
.scc_tbase
= dpaddr
+sizeof(cbd_t
);
486 /* Initialize Tx/Rx parameters.
488 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
490 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_CH_SCC
, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
492 while (cp
->cp_cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
495 up
->scc_genscc
.scc_rfcr
= SCC_EB
| 0x05;
496 up
->scc_genscc
.scc_tfcr
= SCC_EB
| 0x05;
498 up
->scc_genscc
.scc_mrblr
= 1; /* Single character receive */
499 up
->scc_maxidl
= 0; /* disable max idle */
500 up
->scc_brkcr
= 1; /* send one break character on stop TX */
508 up
->scc_char1
= 0x8000;
509 up
->scc_char2
= 0x8000;
510 up
->scc_char3
= 0x8000;
511 up
->scc_char4
= 0x8000;
512 up
->scc_char5
= 0x8000;
513 up
->scc_char6
= 0x8000;
514 up
->scc_char7
= 0x8000;
515 up
->scc_char8
= 0x8000;
516 up
->scc_rccm
= 0xc0ff;
518 /* Set low latency / small fifo.
520 sp
->scc_gsmrh
= SCC_GSMRH_RFW
;
522 /* Set SCC(x) clock mode to 16x
523 * See 8xx_io/commproc.c for details.
528 /* Set UART mode, clock divider 16 on Tx and Rx
530 sp
->scc_gsmrl
&= ~0xF;
532 (SCC_GSMRL_MODE_UART
| SCC_GSMRL_TDCR_16
| SCC_GSMRL_RDCR_16
);
535 sp
->scc_psmr
|= SCU_PSMR_CL
;
537 /* Mask all interrupts and remove anything pending.
540 sp
->scc_scce
= 0xffff;
541 sp
->scc_dsr
= 0x7e7e;
542 sp
->scc_psmr
= 0x3000;
544 /* Make the first buffer the only buffer.
546 tbdf
->cbd_sc
|= BD_SC_WRAP
;
547 rbdf
->cbd_sc
|= BD_SC_EMPTY
| BD_SC_WRAP
;
549 /* Enable transmitter/receiver.
551 sp
->scc_gsmrl
|= (SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
557 scc_putc(const char c
)
559 volatile cbd_t
*tbdf
;
561 volatile scc_uart_t
*up
;
562 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
563 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
565 #ifdef CONFIG_MODEM_SUPPORT
573 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
575 tbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_tbase
];
577 /* Wait for last character to go.
580 buf
= (char *)tbdf
->cbd_bufaddr
;
583 tbdf
->cbd_datlen
= 1;
584 tbdf
->cbd_sc
|= BD_SC_READY
;
587 while (tbdf
->cbd_sc
& BD_SC_READY
) {
594 scc_puts (const char *s
)
604 volatile cbd_t
*rbdf
;
605 volatile unsigned char *buf
;
606 volatile scc_uart_t
*up
;
607 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
608 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
611 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
613 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
615 /* Wait for character to show up.
617 buf
= (unsigned char *)rbdf
->cbd_bufaddr
;
619 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
623 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
631 volatile cbd_t
*rbdf
;
632 volatile scc_uart_t
*up
;
633 volatile immap_t
*im
= (immap_t
*)CFG_IMMR
;
634 volatile cpm8xx_t
*cpmp
= &(im
->im_cpm
);
636 up
= (scc_uart_t
*)&cpmp
->cp_dparam
[PROFF_SCC
];
638 rbdf
= (cbd_t
*)&cpmp
->cp_dpmem
[up
->scc_genscc
.scc_rbase
];
640 return(!(rbdf
->cbd_sc
& BD_SC_EMPTY
));
643 struct serial_device serial_scc_device
=
655 #endif /* CONFIG_8xx_CONS_SCCx */
657 #ifdef CONFIG_MODEM_SUPPORT
658 void disable_putc(void)
663 void enable_putc(void)
669 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
672 kgdb_serial_init(void)
676 if (strcmp(default_serial_console()->ctlr
, "SMC") == 0)
678 #if defined(CONFIG_8xx_CONS_SMC1)
680 #elif defined(CONFIG_8xx_CONS_SMC2)
684 else if (strcmp(default_serial_console()->ctlr
, "SMC") == 0)
686 #if defined(CONFIG_8xx_CONS_SCC1)
688 #elif defined(CONFIG_8xx_CONS_SCC2)
690 #elif defined(CONFIG_8xx_CONS_SCC3)
692 #elif defined(CONFIG_8xx_CONS_SCC4)
699 serial_printf("[on %s%d] ", default_serial_console()->ctlr
, i
);
710 putDebugStr (const char *str
)
718 return serial_getc();
722 kgdb_interruptible (int yes
)
726 #endif /* CFG_CMD_KGDB */
728 #endif /* CONFIG_8xx_CONS_NONE */