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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/ppc4xx/40x_spd_sdram.c
2 * cpu/ppc4xx/40x_spd_sdram.c
3 * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
4 * SDRAM controller. Those are all current 405 PPC's.
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
26 * See file CREDITS for list of people who contributed to this
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
46 #include <asm/processor.h>
50 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
55 #ifndef CONFIG_SYS_I2C_SPEED
56 #define CONFIG_SYS_I2C_SPEED 50000
59 #ifndef CONFIG_SYS_I2C_SLAVE
60 #define CONFIG_SYS_I2C_SLAVE 0xFE
63 #define ONE_BILLION 1000000000
65 #define SDRAM0_CFG_DCE 0x80000000
66 #define SDRAM0_CFG_SRE 0x40000000
67 #define SDRAM0_CFG_PME 0x20000000
68 #define SDRAM0_CFG_MEMCHK 0x10000000
69 #define SDRAM0_CFG_REGEN 0x08000000
70 #define SDRAM0_CFG_ECCDD 0x00400000
71 #define SDRAM0_CFG_EMDULR 0x00200000
72 #define SDRAM0_CFG_DRW_SHIFT (31-6)
73 #define SDRAM0_CFG_BRPF_SHIFT (31-8)
75 #define SDRAM0_TR_CASL_SHIFT (31-8)
76 #define SDRAM0_TR_PTA_SHIFT (31-13)
77 #define SDRAM0_TR_CTP_SHIFT (31-15)
78 #define SDRAM0_TR_LDF_SHIFT (31-17)
79 #define SDRAM0_TR_RFTA_SHIFT (31-29)
80 #define SDRAM0_TR_RCD_SHIFT (31-31)
82 #define SDRAM0_RTR_SHIFT (31-15)
83 #define SDRAM0_ECCCFG_SHIFT (31-11)
85 /* SDRAM0_CFG enable macro */
86 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
88 #define SDRAM0_BXCR_SZ_MASK 0x000e0000
89 #define SDRAM0_BXCR_AM_MASK 0x0000e000
91 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
92 #define SDRAM0_BXCR_AM_SHIFT (31-18)
94 #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
95 #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
97 #ifdef CONFIG_SPDDRAM_SILENT
98 # define SPD_ERR(x) do { return 0; } while (0)
100 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
103 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
105 /* function prototypes */
106 int spd_read(uint addr
);
110 * This function is reading data from the DIMM module EEPROM over the SPD bus
111 * and uses that to program the sdram controller.
113 * This works on boards that has the same schematics that the AMCC walnut has.
115 * Input: null for default I2C spd functions or a pointer to a custom function
116 * returning spd_data.
119 long int spd_sdram(int(read_spd
)(uint addr
))
122 int total_size
,bank_size
,bank_code
;
127 int sdram0_pmit
=0x07c00000;
128 #ifndef CONFIG_405EP /* not on PPC405EP */
129 int sdram0_besr0
= -1;
130 int sdram0_besr1
= -1;
131 int sdram0_eccesr
= -1;
151 PPC4xx_SYS_INFO sys_info
;
152 unsigned long bus_period_x_10
;
157 get_sys_info(&sys_info
);
158 bus_period_x_10
= ONE_BILLION
/ (sys_info
.freqPLB
/ 10);
163 * Make sure I2C controller is initialized
166 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
169 /* Make shure we are using SDRAM */
170 if (read_spd(2) != 0x04) {
171 SPD_ERR("SDRAM - non SDRAM memory module found\n");
174 /* ------------------------------------------------------------------
175 * configure memory timing register
178 * 27 IN Row Precharge Time ( t RP)
179 * 29 MIN RAS to CAS Delay ( t RCD)
180 * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
181 * -------------------------------------------------------------------*/
184 * first figure out which cas latency mode to use
185 * use the min supported mode
188 tmp
= read_spd(127) & 0x6;
189 if (tmp
== 0x02) { /* only cas = 2 supported */
191 /* t_ck = read_spd(9); */
192 /* t_ac = read_spd(10); */
193 } else if (tmp
== 0x04) { /* only cas = 3 supported */
195 /* t_ck = read_spd(9); */
196 /* t_ac = read_spd(10); */
197 } else if (tmp
== 0x06) { /* 2,3 supported, so use 2 */
199 /* t_ck = read_spd(23); */
200 /* t_ac = read_spd(24); */
202 SPD_ERR("SDRAM - unsupported CAS latency \n");
205 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
208 t_rcd
= read_spd(29);
209 t_ras
= read_spd(30);
212 /* The following timing calcs subtract 1 before deviding.
213 * this has effect of using ceiling instead of floor rounding,
214 * and also subtracting 1 to convert number to reg value
217 sdram0_tr
= (min_cas
- 1) << SDRAM0_TR_CASL_SHIFT
;
219 sdram0_tr
|= ((((t_rp
- 1) * 10)/bus_period_x_10
) & 0x3) << SDRAM0_TR_PTA_SHIFT
;
221 tmp
= (((t_rc
- t_rcd
- t_rp
-1) * 10) / bus_period_x_10
) & 0x3;
224 sdram0_tr
|= tmp
<< SDRAM0_TR_CTP_SHIFT
;
225 /* set LDF = 2 cycles, reg value = 1 */
226 sdram0_tr
|= 1 << SDRAM0_TR_LDF_SHIFT
;
227 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
228 tmp
= (((t_rc
- 1) * 10) / bus_period_x_10
) - 3;
233 sdram0_tr
|= tmp
<< SDRAM0_TR_RFTA_SHIFT
;
234 /* set RCD = t_rcd/bus_period*/
235 sdram0_tr
|= ((((t_rcd
- 1) * 10) / bus_period_x_10
) &0x3) << SDRAM0_TR_RCD_SHIFT
;
238 /*------------------------------------------------------------------
239 * configure RTR register
240 * -------------------------------------------------------------------*/
243 tmp
= read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
264 SPD_ERR("SDRAM - Bad refresh period \n");
266 /* convert from nsec to bus cycles */
267 tmp
= (tmp
* 10) / bus_period_x_10
;
268 sdram0_rtr
= (tmp
& 0x3ff8) << SDRAM0_RTR_SHIFT
;
270 /*------------------------------------------------------------------
271 * determine the number of banks used
272 * -------------------------------------------------------------------*/
273 /* byte 7:6 is module data width */
274 if (read_spd(7) != 0)
275 SPD_ERR("SDRAM - unsupported module width\n");
278 SPD_ERR("SDRAM - unsupported module width\n");
280 bank_cnt
= 1; /* one bank per sdram side */
282 bank_cnt
= 2; /* need two banks per side */
284 bank_cnt
= 4; /* need four banks per side */
286 SPD_ERR("SDRAM - unsupported module width\n");
288 /* byte 5 is the module row count (refered to as dimm "sides") */
297 bank_cnt
= 8; /* 8 is an error code */
299 if (bank_cnt
> 4) /* we only have 4 banks to work with */
300 SPD_ERR("SDRAM - unsupported module rows for this width\n");
302 /* now check for ECC ability of module. We only support ECC
303 * on 32 bit wide devices with 8 bit ECC.
305 if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
306 sdram0_ecccfg
= 0xf << SDRAM0_ECCCFG_SHIFT
;
313 /*------------------------------------------------------------------
314 * calculate total size
315 * -------------------------------------------------------------------*/
316 /* calculate total size and do sanity check */
318 total_size
= 1 << 22; /* total_size = 4MB */
319 /* now multiply 4M by the smallest device row density */
320 /* note that we don't support asymetric rows */
321 while (((tmp
& 0x0001) == 0) && (tmp
!= 0)) {
322 total_size
= total_size
<< 1;
325 total_size
*= read_spd(5); /* mult by module rows (dimm sides) */
327 /*------------------------------------------------------------------
328 * map rows * cols * banks to a mode
329 * -------------------------------------------------------------------*/
342 SPD_ERR("SDRAM - unsupported mode\n");
355 SPD_ERR("SDRAM - unsupported mode\n");
365 if (read_spd(17) == 2)
366 mode
= 6; /* mode 7 */
368 mode
= 2; /* mode 3 */
371 mode
= 2; /* mode 3 */
374 SPD_ERR("SDRAM - unsupported mode\n");
378 SPD_ERR("SDRAM - unsupported mode\n");
381 /*------------------------------------------------------------------
382 * using the calculated values, compute the bank
383 * config register values.
384 * -------------------------------------------------------------------*/
389 /* compute the size of each bank */
390 bank_size
= total_size
/ bank_cnt
;
391 /* convert bank size to bank size code for ppc4xx
392 by takeing log2(bank_size) - 22 */
393 tmp
= bank_size
; /* start with tmp = bank_size */
394 bank_code
= 0; /* and bank_code = 0 */
395 while (tmp
> 1) { /* this takes log2 of tmp */
396 bank_code
++; /* and stores result in bank_code */
398 } /* bank_code is now log2(bank_size) */
399 bank_code
-= 22; /* subtract 22 to get the code */
401 tmp
= SDRAM0_BXCR_SZ(bank_code
) | SDRAM0_BXCR_AM(mode
) | 1;
402 sdram0_b0cr
= (bank_size
* 0) | tmp
;
403 #ifndef CONFIG_405EP /* not on PPC405EP */
405 sdram0_b2cr
= (bank_size
* 1) | tmp
;
407 sdram0_b1cr
= (bank_size
* 2) | tmp
;
409 sdram0_b3cr
= (bank_size
* 3) | tmp
;
411 /* PPC405EP chip only supports two SDRAM banks */
413 sdram0_b1cr
= (bank_size
* 1) | tmp
;
415 total_size
= 2 * bank_size
;
419 * enable sdram controller DCE=1
420 * enable burst read prefetch to 32 bytes BRPF=2
421 * leave other functions off
424 /*------------------------------------------------------------------
425 * now that we've done our calculations, we are ready to
426 * program all the registers.
427 * -------------------------------------------------------------------*/
429 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
430 /* disable memcontroller so updates work */
431 mtsdram0( mem_mcopt1
, 0 );
433 #ifndef CONFIG_405EP /* not on PPC405EP */
434 mtsdram0( mem_besra
, sdram0_besr0
);
435 mtsdram0( mem_besrb
, sdram0_besr1
);
436 mtsdram0( mem_ecccf
, sdram0_ecccfg
);
437 mtsdram0( mem_eccerr
, sdram0_eccesr
);
439 mtsdram0( mem_rtr
, sdram0_rtr
);
440 mtsdram0( mem_pmit
, sdram0_pmit
);
441 mtsdram0( mem_mb0cf
, sdram0_b0cr
);
442 mtsdram0( mem_mb1cf
, sdram0_b1cr
);
443 #ifndef CONFIG_405EP /* not on PPC405EP */
444 mtsdram0( mem_mb2cf
, sdram0_b2cr
);
445 mtsdram0( mem_mb3cf
, sdram0_b3cr
);
447 mtsdram0( mem_sdtr1
, sdram0_tr
);
449 /* SDRAM have a power on delay, 500 micro should do */
451 sdram0_cfg
= SDRAM0_CFG_DCE
| SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD
| SDRAM0_CFG_EMDULR
;
453 sdram0_cfg
|= SDRAM0_CFG_MEMCHK
;
454 mtsdram0(mem_mcopt1
, sdram0_cfg
);
459 int spd_read(uint addr
)
463 if (i2c_read(SPD_EEPROM_ADDRESS
, addr
, 1, data
, 1) == 0)
469 #endif /* CONFIG_SPD_EEPROM */