2 * (C) Copyright 2007-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
30 gpio_param_s
const gpio_tab
[GPIO_GROUP_MAX
][GPIO_MAX
] = CONFIG_SYS_4xx_GPIO_TABLE
;
33 #if defined(GPIO0_OSRL)
34 /* Only some 4xx variants support alternate funtions on the GPIO's */
35 void gpio_config(int pin
, int in_out
, int gpio_alt
, int out_val
)
44 if (pin
>= GPIO_MAX
) {
49 if (pin
>= GPIO_MAX
/2) {
51 pin2
= (pin
- GPIO_MAX
/2) << 1;
54 mask
= 0x80000000 >> pin
;
55 mask2
= 0xc0000000 >> pin2
;
57 /* first set TCR to 0 */
58 out_be32((void *)GPIO0_TCR
+ offs
, in_be32((void *)GPIO0_TCR
+ offs
) & ~mask
);
60 if (in_out
== GPIO_OUT
) {
61 val
= in_be32((void *)GPIO0_OSRL
+ offs
+ offs2
) & ~mask2
;
64 val
|= GPIO_ALT1_SEL
>> pin2
;
67 val
|= GPIO_ALT2_SEL
>> pin2
;
70 val
|= GPIO_ALT3_SEL
>> pin2
;
73 out_be32((void *)GPIO0_OSRL
+ offs
+ offs2
, val
);
75 /* setup requested output value */
76 if (out_val
== GPIO_OUT_0
)
77 out_be32((void *)GPIO0_OR
+ offs
,
78 in_be32((void *)GPIO0_OR
+ offs
) & ~mask
);
79 else if (out_val
== GPIO_OUT_1
)
80 out_be32((void *)GPIO0_OR
+ offs
,
81 in_be32((void *)GPIO0_OR
+ offs
) | mask
);
83 /* now configure TCR to drive output if selected */
84 out_be32((void *)GPIO0_TCR
+ offs
,
85 in_be32((void *)GPIO0_TCR
+ offs
) | mask
);
87 val
= in_be32((void *)GPIO0_ISR1L
+ offs
+ offs2
) & ~mask2
;
88 val
|= GPIO_IN_SEL
>> pin2
;
89 out_be32((void *)GPIO0_ISR1L
+ offs
+ offs2
, val
);
92 #endif /* GPIO_OSRL */
94 void gpio_write_bit(int pin
, int val
)
98 if (pin
>= GPIO_MAX
) {
104 out_be32((void *)GPIO0_OR
+ offs
,
105 in_be32((void *)GPIO0_OR
+ offs
) | GPIO_VAL(pin
));
107 out_be32((void *)GPIO0_OR
+ offs
,
108 in_be32((void *)GPIO0_OR
+ offs
) & ~GPIO_VAL(pin
));
111 int gpio_read_out_bit(int pin
)
115 if (pin
>= GPIO_MAX
) {
120 return (in_be32((void *)GPIO0_OR
+ offs
) & GPIO_VAL(pin
) ? 1 : 0);
123 int gpio_read_in_bit(int pin
)
127 if (pin
>= GPIO_MAX
) {
132 return (in_be32((void *)GPIO0_IR
+ offs
) & GPIO_VAL(pin
) ? 1 : 0);
135 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
136 void gpio_set_chip_configuration(void)
138 unsigned char i
=0, j
=0, offs
=0, gpio_core
;
139 unsigned long reg
, core_add
;
141 for (gpio_core
=0; gpio_core
<GPIO_GROUP_MAX
; gpio_core
++) {
144 /* GPIO config of the GPIOs 0 to 31 */
145 for (i
=0; i
<GPIO_MAX
; i
++, j
++) {
146 if (i
== GPIO_MAX
/2) {
151 core_add
= gpio_tab
[gpio_core
][i
].add
;
153 if ((gpio_tab
[gpio_core
][i
].in_out
== GPIO_IN
) ||
154 (gpio_tab
[gpio_core
][i
].in_out
== GPIO_BI
)) {
156 switch (gpio_tab
[gpio_core
][i
].alt_nb
) {
161 reg
= in_be32((void *)GPIO_IS1(core_add
+offs
))
162 & ~(GPIO_MASK
>> (j
*2));
163 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
164 out_be32((void *)GPIO_IS1(core_add
+offs
), reg
);
168 reg
= in_be32((void *)GPIO_IS2(core_add
+offs
))
169 & ~(GPIO_MASK
>> (j
*2));
170 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
171 out_be32((void *)GPIO_IS2(core_add
+offs
), reg
);
175 reg
= in_be32((void *)GPIO_IS3(core_add
+offs
))
176 & ~(GPIO_MASK
>> (j
*2));
177 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
178 out_be32((void *)GPIO_IS3(core_add
+offs
), reg
);
183 if ((gpio_tab
[gpio_core
][i
].in_out
== GPIO_OUT
) ||
184 (gpio_tab
[gpio_core
][i
].in_out
== GPIO_BI
)) {
186 u32 gpio_alt_sel
= 0;
188 switch (gpio_tab
[gpio_core
][i
].alt_nb
) {
194 * else -> don't touch
196 reg
= in_be32((void *)GPIO_OR(core_add
));
197 if (gpio_tab
[gpio_core
][i
].out_val
== GPIO_OUT_1
)
198 reg
|= (0x80000000 >> (i
));
199 else if (gpio_tab
[gpio_core
][i
].out_val
== GPIO_OUT_0
)
200 reg
&= ~(0x80000000 >> (i
));
201 out_be32((void *)GPIO_OR(core_add
), reg
);
203 reg
= in_be32((void *)GPIO_TCR(core_add
)) |
205 out_be32((void *)GPIO_TCR(core_add
), reg
);
207 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
208 & ~(GPIO_MASK
>> (j
*2));
209 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
210 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
211 & ~(GPIO_MASK
>> (j
*2));
212 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
216 gpio_alt_sel
= GPIO_ALT1_SEL
;
220 gpio_alt_sel
= GPIO_ALT2_SEL
;
224 gpio_alt_sel
= GPIO_ALT3_SEL
;
228 if (0 != gpio_alt_sel
) {
229 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
230 & ~(GPIO_MASK
>> (j
*2));
231 reg
= reg
| (gpio_alt_sel
>> (j
*2));
232 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
234 if (gpio_tab
[gpio_core
][i
].out_val
== GPIO_OUT_1
) {
235 reg
= in_be32((void *)GPIO_TCR(core_add
))
236 | (0x80000000 >> (i
));
237 out_be32((void *)GPIO_TCR(core_add
), reg
);
238 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
239 & ~(GPIO_MASK
>> (j
*2));
240 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
242 reg
= in_be32((void *)GPIO_TCR(core_add
))
243 & ~(0x80000000 >> (i
));
244 out_be32((void *)GPIO_TCR(core_add
), reg
);
245 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
246 & ~(GPIO_MASK
>> (j
*2));
247 reg
= reg
| (gpio_alt_sel
>> (j
*2));
248 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
255 #endif /* CONFIG_SYS_4xx_GPIO_TABLE */