cpu/ppc4xx/ndfc.c

   1 /*
   2  * Overview:
   3  *   Platform independend driver for NDFC (NanD Flash Controller)
   4  *   integrated into EP440 cores
   5  *
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * Based on original work by
  10  *      Thomas Gleixner
  11  *      Copyright 2006 IBM
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33
  34 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
  35         (defined(CONFIG_440EP) || defined(CONFIG_440GR) ||           \
  36          defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||         \
  37          defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||           \
  38          defined(CONFIG_460EX) || defined(CONFIG_460GT))
  39
  40 #include <nand.h>
  41 #include <linux/mtd/ndfc.h>
  42 #include <linux/mtd/nand_ecc.h>
  43 #include <asm/processor.h>
  44 #include <asm/io.h>
  45 #include <ppc4xx.h>
  46
  47 static u8 hwctl = 0;
  48
  49 static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
  50 {
  51         switch (cmd) {
  52         case NAND_CTL_SETCLE:
  53                 hwctl |= 0x1;
  54                 break;
  55
  56         case NAND_CTL_CLRCLE:
  57                 hwctl &= ~0x1;
  58                 break;
  59
  60         case NAND_CTL_SETALE:
  61                 hwctl |= 0x2;
  62                 break;
  63
  64         case NAND_CTL_CLRALE:
  65                 hwctl &= ~0x2;
  66                 break;
  67         }
  68 }
  69
  70 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
  71 {
  72         struct nand_chip *this = mtdinfo->priv;
  73         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  74
  75         if (hwctl & 0x1)
  76                 out_8((u8 *)(base + NDFC_CMD), byte);
  77         else if (hwctl & 0x2)
  78                 out_8((u8 *)(base + NDFC_ALE), byte);
  79         else
  80                 out_8((u8 *)(base + NDFC_DATA), byte);
  81 }
  82
  83 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
  84 {
  85         struct nand_chip *this = mtdinfo->priv;
  86         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  87
  88         return (in_8((u8 *)(base + NDFC_DATA)));
  89 }
  90
  91 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  92 {
  93         struct nand_chip *this = mtdinfo->priv;
  94         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
  95
  96         while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
  97                 ;
  98
  99         return 1;
 100 }
 101
 102 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
 103 {
 104         struct nand_chip *this = mtdinfo->priv;
 105         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 106         u32 ccr;
 107
 108         ccr = in_be32((u32 *)(base + NDFC_CCR));
 109         ccr |= NDFC_CCR_RESET_ECC;
 110         out_be32((u32 *)(base + NDFC_CCR), ccr);
 111 }
 112
 113 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 114                               const u_char *dat, u_char *ecc_code)
 115 {
 116         struct nand_chip *this = mtdinfo->priv;
 117         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 118         u32 ecc;
 119         u8 *p = (u8 *)&ecc;
 120
 121         ecc = in_be32((u32 *)(base + NDFC_ECC));
 122
 123         /* The NDFC uses Smart Media (SMC) bytes order
 124          */
 125         ecc_code[0] = p[1];
 126         ecc_code[1] = p[2];
 127         ecc_code[2] = p[3];
 128
 129         return 0;
 130 }
 131
 132 /*
 133  * Speedups for buffer read/write/verify
 134  *
 135  * NDFC allows 32bit read/write of data. So we can speed up the buffer
 136  * functions. No further checking, as nand_base will always read/write
 137  * page aligned.
 138  */
 139 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 140 {
 141         struct nand_chip *this = mtdinfo->priv;
 142         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 143         uint32_t *p = (uint32_t *) buf;
 144
 145         for (;len > 0; len -= 4)
 146                 *p++ = in_be32((u32 *)(base + NDFC_DATA));
 147 }
 148
 149 #ifndef CONFIG_NAND_SPL
 150 /*
 151  * Don't use these speedup functions in NAND boot image, since the image
 152  * has to fit into 4kByte.
 153  */
 154 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 155 {
 156         struct nand_chip *this = mtdinfo->priv;
 157         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 158         uint32_t *p = (uint32_t *) buf;
 159
 160         for (; len > 0; len -= 4)
 161                 out_be32((u32 *)(base + NDFC_DATA), *p++);
 162 }
 163
 164 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 165 {
 166         struct nand_chip *this = mtdinfo->priv;
 167         ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
 168         uint32_t *p = (uint32_t *) buf;
 169
 170         for (; len > 0; len -= 4)
 171                 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
 172                         return -1;
 173
 174         return 0;
 175 }
 176 #endif /* #ifndef CONFIG_NAND_SPL */
 177
 178 void board_nand_select_device(struct nand_chip *nand, int chip)
 179 {
 180         /*
 181          * Don't use "chip" to address the NAND device,
 182          * generate the cs from the address where it is encoded.
 183          */
 184         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 185         ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
 186
 187         /* Set NandFlash Core Configuration Register */
 188         /* 1 col x 2 rows */
 189         out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
 190 }
 191
 192 int board_nand_init(struct nand_chip *nand)
 193 {
 194         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 195         ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
 196
 197         nand->hwcontrol  = ndfc_hwcontrol;
 198         nand->read_byte  = ndfc_read_byte;
 199         nand->read_buf   = ndfc_read_buf;
 200         nand->write_byte = ndfc_write_byte;
 201         nand->dev_ready  = ndfc_dev_ready;
 202
 203         nand->eccmode = NAND_ECC_HW3_256;
 204         nand->enable_hwecc = ndfc_enable_hwecc;
 205         nand->calculate_ecc = ndfc_calculate_ecc;
 206         nand->correct_data = nand_correct_data;
 207
 208 #ifndef CONFIG_NAND_SPL
 209         nand->write_buf  = ndfc_write_buf;
 210         nand->verify_buf = ndfc_verify_buf;
 211 #else
 212         /*
 213          * Setup EBC (CS0 only right now)
 214          */
 215         mtebc(EBC0_CFG, 0xb8400000);
 216
 217         mtebc(pb0cr, CFG_EBC_PB0CR);
 218         mtebc(pb0ap, CFG_EBC_PB0AP);
 219 #endif
 220
 221         /*
 222          * Select required NAND chip in NDFC
 223          */
 224         board_nand_select_device(nand, cs);
 225         out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
 226
 227         return 0;
 228 }
 229
 230 #endif