cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/pxa-regs.h>
  34
  35 .globl _start
  36 _start: b       reset
  37         ldr     pc, _undefined_instruction
  38         ldr     pc, _software_interrupt
  39         ldr     pc, _prefetch_abort
  40         ldr     pc, _data_abort
  41         ldr     pc, _not_used
  42         ldr     pc, _irq
  43         ldr     pc, _fiq
  44
  45 _undefined_instruction: .word undefined_instruction
  46 _software_interrupt:    .word software_interrupt
  47 _prefetch_abort:        .word prefetch_abort
  48 _data_abort:            .word data_abort
  49 _not_used:              .word not_used
  50 _irq:                   .word irq
  51 _fiq:                   .word fiq
  52
  53         .balignl 16,0xdeadbeef
  54
  55
  56 /*
  57  * Startup Code (reset vector)
  58  *
  59  * do important init only if we don't start from RAM!
  60  * - relocate armboot to RAM
  61  * - setup stack
  62  * - jump to second stage
  63  */
  64
  65 _TEXT_BASE:
  66         .word   TEXT_BASE
  67
  68 .globl _armboot_start
  69 _armboot_start:
  70         .word _start
  71
  72 /*
  73  * These are defined in the board-specific linker script.
  74  */
  75 .globl _bss_start
  76 _bss_start:
  77         .word __bss_start
  78
  79 .globl _bss_end
  80 _bss_end:
  81         .word _end
  82
  83 #ifdef CONFIG_USE_IRQ
  84 /* IRQ stack memory (calculated at run-time) */
  85 .globl IRQ_STACK_START
  86 IRQ_STACK_START:
  87         .word   0x0badc0de
  88
  89 /* IRQ stack memory (calculated at run-time) */
  90 .globl FIQ_STACK_START
  91 FIQ_STACK_START:
  92         .word 0x0badc0de
  93 #endif /* CONFIG_USE_IRQ */
  94
  95
  96 /****************************************************************************/
  97 /*                                                                          */
  98 /* the actual reset code                                                    */
  99 /*                                                                          */
 100 /****************************************************************************/
 101
 102 reset:
 103         mrs     r0,cpsr                 /* set the CPU to SVC32 mode        */
 104         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 105         orr     r0,r0,#0x13
 106         msr     cpsr,r0
 107
 108         /*
 109          * we do sys-critical inits only at reboot,
 110          * not when booting from RAM!
 111          */
 112 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 113         bl      cpu_init_crit           /* we do sys-critical inits         */
 114 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
 115
 116 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 117 relocate:                               /* relocate U-Boot to RAM           */
 118         adr     r0, _start              /* r0 <- current position of code   */
 119         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 120         cmp     r0, r1                  /* don't reloc during debug         */
 121         beq     stack_setup
 122
 123         ldr     r2, _armboot_start
 124         ldr     r3, _bss_start
 125         sub     r2, r3, r2              /* r2 <- size of armboot            */
 126         add     r2, r0, r2              /* r2 <- source end address         */
 127
 128 copy_loop:
 129         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 130         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 131         cmp     r0, r2                  /* until source end addreee [r2]    */
 132         ble     copy_loop
 133 #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
 134
 135         /* Set up the stack                                                 */
 136 stack_setup:
 137         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 138         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 139         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 140 #ifdef CONFIG_USE_IRQ
 141         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 142 #endif /* CONFIG_USE_IRQ */
 143         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 144
 145 clear_bss:
 146         ldr     r0, _bss_start          /* find start of bss segment        */
 147         ldr     r1, _bss_end            /* stop here                        */
 148         mov     r2, #0x00000000         /* clear                            */
 149
 150 clbss_l:str     r2, [r0]                /* clear loop...                    */
 151         add     r0, r0, #4
 152         cmp     r0, r1
 153         ble     clbss_l
 154
 155         ldr     pc, _start_armboot
 156
 157 _start_armboot: .word start_armboot
 158
 159
 160 /****************************************************************************/
 161 /*                                                                          */
 162 /* CPU_init_critical registers                                              */
 163 /*                                                                          */
 164 /* - setup important registers                                              */
 165 /* - setup memory timing                                                    */
 166 /*                                                                          */
 167 /****************************************************************************/
 168 /* mk@tbd: Fix this! */
 169 #if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
 170 #undef ICMR
 171 #undef OSMR3
 172 #undef OSCR
 173 #undef OWER
 174 #undef OIER
 175 #endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
 176 #ifdef CONFIG_PXA250
 177 #undef RCSR
 178 #undef CCCR
 179 #endif /* CONFIG_PXA250 */
 180
 181 /* Interrupt-Controller base address                                        */
 182 IC_BASE:           .word           0x40d00000
 183 #define ICMR    0x04
 184
 185 /* Reset-Controller */
 186 RST_BASE:       .word   0x40f00030
 187 #define RCSR    0x00
 188
 189 /* Operating System Timer */
 190 OSTIMER_BASE:   .word   0x40a00000
 191 #define OSMR3   0x0C
 192 #define OSCR    0x10
 193 #define OWER    0x18
 194 #define OIER    0x1C
 195
 196 /* Clock Manager Registers                                                  */
 197 #ifdef CONFIG_CPU_MONAHANS
 198 # ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
 199 #  error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
 200 # endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
 201 # ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
 202 #  define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
 203 # endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
 204 #else /* !CONFIG_CPU_MONAHANS */
 205 #ifdef CFG_CPUSPEED
 206 CC_BASE:        .word   0x41300000
 207 #define CCCR    0x00
 208 cpuspeed:       .word   CFG_CPUSPEED
 209 #else /* !CFG_CPUSPEED */
 210 #error "You have to define CFG_CPUSPEED!!"
 211 #endif /* CFG_CPUSPEED */
 212 #endif /* CONFIG_CPU_MONAHANS */
 213
 214         /* takes care the CP15 update has taken place */
 215         .macro CPWAIT reg
 216         mrc  p15,0,\reg,c2,c0,0
 217         mov  \reg,\reg
 218         sub  pc,pc,#4
 219         .endm
 220
 221 cpu_init_crit:
 222
 223         /* mask all IRQs                                                    */
 224 #ifndef CONFIG_CPU_MONAHANS
 225         ldr     r0, IC_BASE
 226         mov     r1, #0x00
 227         str     r1, [r0, #ICMR]
 228 #else /* CONFIG_CPU_MONAHANS */
 229         /* Step 1 - Enable CP6 permission */
 230         mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
 231         orr     r1, r1, #0x40
 232                 mcr     p15, 0, r1, c15, c1, 0
 233         CPWAIT  r1
 234
 235         /* Step 2 - Mask ICMR & ICMR2 */
 236         mov     r1, #0
 237         mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 238         mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
 239
 240         /* turn off all clocks but the ones we will definitly require */
 241         ldr     r1, =CKENA
 242         ldr     r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
 243         str     r2, [r1]
 244         ldr     r1, =CKENB
 245         ldr     r2, =(CKENB_6_IRQ)
 246         str     r2, [r1]
 247 #endif /* !CONFIG_CPU_MONAHANS */
 248
 249         /* set clock speed */
 250 #ifdef CONFIG_CPU_MONAHANS
 251         ldr     r0, =ACCR
 252         ldr     r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
 253         str     r1, [r0]
 254 #else /* !CONFIG_CPU_MONAHANS */
 255 #ifdef CFG_CPUSPEED
 256         ldr     r0, CC_BASE
 257         ldr     r1, cpuspeed
 258         str     r1, [r0, #CCCR]
 259         mov     r0, #2
 260         mcr     p14, 0, r0, c6, c0, 0
 261
 262 setspeed_done:
 263
 264 #endif /* CFG_CPUSPEED */
 265 #endif /* CONFIG_CPU_MONAHANS */
 266
 267         /*
 268          * before relocating, we have to setup RAM timing
 269          * because memory timing is board-dependend, you will
 270          * find a lowlevel_init.S in your board directory.
 271          */
 272         mov     ip,     lr
 273         bl      lowlevel_init
 274         mov     lr,     ip
 275
 276         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 277         /* mk: hmm, this is not in the monahans docs, leave it now but
 278          *     check here if it doesn't work :-) */
 279
 280         ldr     r0, =0x2001             /* enable access to all coproc.     */
 281         mcr     p15, 0, r0, c15, c1, 0
 282         CPWAIT r0
 283
 284         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 285         CPWAIT r0
 286
 287         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 288         CPWAIT r0
 289
 290         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 291         CPWAIT r0
 292
 293         /* Enable the Icache                                                */
 294 /*
 295         mrc     p15, 0, r0, c1, c0, 0
 296         orr     r0, r0, #0x1800
 297         mcr     p15, 0, r0, c1, c0, 0
 298         CPWAIT
 299 */
 300         mov     pc, lr
 301
 302
 303 /****************************************************************************/
 304 /*                                                                          */
 305 /* Interrupt handling                                                       */
 306 /*                                                                          */
 307 /****************************************************************************/
 308
 309 /* IRQ stack frame                                                          */
 310
 311 #define S_FRAME_SIZE    72
 312
 313 #define S_OLD_R0        68
 314 #define S_PSR           64
 315 #define S_PC            60
 316 #define S_LR            56
 317 #define S_SP            52
 318
 319 #define S_IP            48
 320 #define S_FP            44
 321 #define S_R10           40
 322 #define S_R9            36
 323 #define S_R8            32
 324 #define S_R7            28
 325 #define S_R6            24
 326 #define S_R5            20
 327 #define S_R4            16
 328 #define S_R3            12
 329 #define S_R2            8
 330 #define S_R1            4
 331 #define S_R0            0
 332
 333 #define MODE_SVC 0x13
 334
 335         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 336
 337         .macro  bad_save_user_regs
 338         sub     sp, sp, #S_FRAME_SIZE
 339         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 340         add     r8, sp, #S_PC
 341
 342         ldr     r2, _armboot_start
 343         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 344         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 345         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 346         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 347
 348         add     r5, sp, #S_SP
 349         mov     r1, lr
 350         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 351         mov     r0, sp
 352         .endm
 353
 354
 355         /* use irq_save_user_regs / irq_restore_user_regs for                */
 356         /* IRQ/FIQ handling                                                  */
 357
 358         .macro  irq_save_user_regs
 359         sub     sp, sp, #S_FRAME_SIZE
 360         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 361         add     r8, sp, #S_PC
 362         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 363         str     lr, [r8, #0]                    /* Save calling PC           */
 364         mrs     r6, spsr
 365         str     r6, [r8, #4]                    /* Save CPSR                 */
 366         str     r0, [r8, #8]                    /* Save OLD_R0               */
 367         mov     r0, sp
 368         .endm
 369
 370         .macro  irq_restore_user_regs
 371         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 372         mov     r0, r0
 373         ldr     lr, [sp, #S_PC]                 @ Get PC
 374         add     sp, sp, #S_FRAME_SIZE
 375         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 376         .endm
 377
 378         .macro get_bad_stack
 379         ldr     r13, _armboot_start             @ setup our mode stack
 380         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 381         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 382
 383         str     lr, [r13]                       @ save caller lr / spsr
 384         mrs     lr, spsr
 385         str     lr, [r13, #4]
 386
 387         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 388         msr     spsr_c, r13
 389         mov     lr, pc
 390         movs    pc, lr
 391         .endm
 392
 393         .macro get_irq_stack                    @ setup IRQ stack
 394         ldr     sp, IRQ_STACK_START
 395         .endm
 396
 397         .macro get_fiq_stack                    @ setup FIQ stack
 398         ldr     sp, FIQ_STACK_START
 399         .endm
 400
 401
 402 /****************************************************************************/
 403 /*                                                                          */
 404 /* exception handlers                                                       */
 405 /*                                                                          */
 406 /****************************************************************************/
 407
 408         .align  5
 409 undefined_instruction:
 410         get_bad_stack
 411         bad_save_user_regs
 412         bl      do_undefined_instruction
 413
 414         .align  5
 415 software_interrupt:
 416         get_bad_stack
 417         bad_save_user_regs
 418         bl      do_software_interrupt
 419
 420         .align  5
 421 prefetch_abort:
 422         get_bad_stack
 423         bad_save_user_regs
 424         bl      do_prefetch_abort
 425
 426         .align  5
 427 data_abort:
 428         get_bad_stack
 429         bad_save_user_regs
 430         bl      do_data_abort
 431
 432         .align  5
 433 not_used:
 434         get_bad_stack
 435         bad_save_user_regs
 436         bl      do_not_used
 437
 438 #ifdef CONFIG_USE_IRQ
 439
 440         .align  5
 441 irq:
 442         get_irq_stack
 443         irq_save_user_regs
 444         bl      do_irq
 445         irq_restore_user_regs
 446
 447         .align  5
 448 fiq:
 449         get_fiq_stack
 450         irq_save_user_regs              /* someone ought to write a more    */
 451         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 452         irq_restore_user_regs
 453
 454 #else /* !CONFIG_USE_IRQ */
 455
 456         .align  5
 457 irq:
 458         get_bad_stack
 459         bad_save_user_regs
 460         bl      do_irq
 461
 462         .align  5
 463 fiq:
 464         get_bad_stack
 465         bad_save_user_regs
 466         bl      do_fiq
 467
 468 #endif /* CONFIG_USE_IRQ */
 469
 470 /****************************************************************************/
 471 /*                                                                          */
 472 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 473 /* perform a watchdog timeout for a soft reset.                             */
 474 /*                                                                          */
 475 /****************************************************************************/
 476
 477         .align  5
 478 .globl reset_cpu
 479
 480         /* FIXME: this code is PXA250 specific. How is this handled on      */
 481         /*        other XScale processors?                                  */
 482
 483 reset_cpu:
 484
 485         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 486
 487         ldr     r0, OSTIMER_BASE
 488         ldr     r1, [r0, #OWER]
 489         orr     r1, r1, #0x0001                 /* bit0: WME                */
 490         str     r1, [r0, #OWER]
 491
 492         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 493         /* the match register as well.                                      */
 494
 495         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 496         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 497         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 498         str     r1, [r0, #OSMR3]
 499
 500 reset_endless:
 501
 502         b       reset_endless