cpu/sa1100/start.S

   1 /*
   2  *  armboot - Startup Code for SA1100 CPU
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28
  29 #include <config.h>
  30 #include <version.h>
  31
  32
  33 /*
  34  *************************************************************************
  35  *
  36  * Jump vector table as in table 3.1 in [1]
  37  *
  38  *************************************************************************
  39  */
  40
  41
  42 .globl _start
  43 _start: b       reset
  44         ldr     pc, _undefined_instruction
  45         ldr     pc, _software_interrupt
  46         ldr     pc, _prefetch_abort
  47         ldr     pc, _data_abort
  48         ldr     pc, _not_used
  49         ldr     pc, _irq
  50         ldr     pc, _fiq
  51
  52 _undefined_instruction: .word undefined_instruction
  53 _software_interrupt:    .word software_interrupt
  54 _prefetch_abort:        .word prefetch_abort
  55 _data_abort:            .word data_abort
  56 _not_used:              .word not_used
  57 _irq:                   .word irq
  58 _fiq:                   .word fiq
  59
  60         .balignl 16,0xdeadbeef
  61
  62
  63 /*
  64  *************************************************************************
  65  *
  66  * Startup Code (reset vector)
  67  *
  68  * do important init only if we don't start from memory!
  69  * relocate armboot to ram
  70  * setup stack
  71  * jump to second stage
  72  *
  73  *************************************************************************
  74  */
  75
  76 _TEXT_BASE:
  77         .word   TEXT_BASE
  78
  79 .globl _armboot_start
  80 _armboot_start:
  81         .word _start
  82
  83 /*
  84  * These are defined in the board-specific linker script.
  85  */
  86 .globl _bss_start
  87 _bss_start:
  88         .word __bss_start
  89
  90 .globl _bss_end
  91 _bss_end:
  92         .word _end
  93
  94 #ifdef CONFIG_USE_IRQ
  95 /* IRQ stack memory (calculated at run-time) */
  96 .globl IRQ_STACK_START
  97 IRQ_STACK_START:
  98         .word   0x0badc0de
  99
 100 /* IRQ stack memory (calculated at run-time) */
 101 .globl FIQ_STACK_START
 102 FIQ_STACK_START:
 103         .word 0x0badc0de
 104 #endif
 105
 106
 107 /*
 108  * the actual reset code
 109  */
 110
 111 reset:
 112         /*
 113          * set the cpu to SVC32 mode
 114          */
 115         mrs     r0,cpsr
 116         bic     r0,r0,#0x1f
 117         orr     r0,r0,#0x13
 118         msr     cpsr,r0
 119
 120         /*
 121          * we do sys-critical inits only at reboot,
 122          * not when booting from ram!
 123          */
 124 #ifdef CONFIG_INIT_CRITICAL
 125         bl      cpu_init_crit
 126 #endif
 127
 128 relocate:                               /* relocate U-Boot to RAM           */
 129         adr     r0, _start              /* r0 <- current position of code   */
 130         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 131         cmp     r0, r1                  /* don't reloc during debug         */
 132         beq     stack_setup
 133
 134         ldr     r2, _armboot_start
 135         ldr     r3, _bss_start
 136         sub     r2, r3, r2              /* r2 <- size of armboot            */
 137         add     r2, r0, r2              /* r2 <- source end address         */
 138
 139 copy_loop:
 140         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 141         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 142         cmp     r0, r2                  /* until source end addreee [r2]    */
 143         ble     copy_loop
 144
 145         /* Set up the stack                                                 */
 146 stack_setup:
 147         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 148         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 149         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 150 #ifdef CONFIG_USE_IRQ
 151         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 152 #endif
 153         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 154
 155 clear_bss:
 156         ldr     r0, _bss_start          /* find start of bss segment        */
 157         add     r0, r0, #4              /* start at first byte of bss       */
 158         ldr     r1, _bss_end            /* stop here                        */
 159         mov     r2, #0x00000000         /* clear                            */
 160
 161 clbss_l:str     r2, [r0]                /* clear loop...                    */
 162         add     r0, r0, #4
 163         cmp     r0, r1
 164         bne     clbss_l
 165
 166         ldr     pc, _start_armboot
 167
 168 _start_armboot: .word start_armboot
 169
 170
 171 /*
 172  *************************************************************************
 173  *
 174  * CPU_init_critical registers
 175  *
 176  * setup important registers
 177  * setup memory timing
 178  *
 179  *************************************************************************
 180  */
 181
 182
 183 /* Interupt-Controller base address */
 184 IC_BASE:        .word   0x90050000
 185 #define ICMR    0x04
 186
 187
 188 /* Reset-Controller */
 189 RST_BASE:               .word   0x90030000
 190 #define RSRR    0x00
 191 #define RCSR    0x04
 192
 193
 194 /* PWR */
 195 PWR_BASE:               .word   0x90020000
 196 #define PSPR    0x08
 197 #define PPCR    0x14
 198 cpuspeed:               .word   CFG_CPUSPEED
 199
 200
 201 cpu_init_crit:
 202         /*
 203          * mask all IRQs
 204          */
 205         ldr     r0, IC_BASE
 206         mov     r1, #0x00
 207         str     r1, [r0, #ICMR]
 208
 209         /* set clock speed */
 210         ldr     r0, PWR_BASE
 211         ldr     r1, cpuspeed
 212         str     r1, [r0, #PPCR]
 213
 214         /*
 215          * before relocating, we have to setup RAM timing
 216          * because memory timing is board-dependend, you will
 217          * find a memsetup.S in your board directory.
 218          */
 219         mov     ip,     lr
 220         bl      memsetup
 221         mov     lr,     ip
 222
 223         /*
 224          * disable MMU stuff and enable I-cache
 225          */
 226         mrc     p15,0,r0,c1,c0
 227         bic     r0, r0, #0x00002000     @ clear bit 13 (X)
 228         bic     r0, r0, #0x0000000f     @ clear bits 3-0 (WCAM)
 229         orr     r0, r0, #0x00001000     @ set bit 12 (I) Icache
 230         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 231         mcr     p15,0,r0,c1,c0
 232
 233         /*
 234          * flush v4 I/D caches
 235          */
 236         mov     r0, #0
 237         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 238         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 239
 240         mov     pc, lr
 241
 242
 243 /*
 244  *************************************************************************
 245  *
 246  * Interrupt handling
 247  *
 248  *************************************************************************
 249  */
 250
 251 @
 252 @ IRQ stack frame.
 253 @
 254 #define S_FRAME_SIZE    72
 255
 256 #define S_OLD_R0        68
 257 #define S_PSR           64
 258 #define S_PC            60
 259 #define S_LR            56
 260 #define S_SP            52
 261
 262 #define S_IP            48
 263 #define S_FP            44
 264 #define S_R10           40
 265 #define S_R9            36
 266 #define S_R8            32
 267 #define S_R7            28
 268 #define S_R6            24
 269 #define S_R5            20
 270 #define S_R4            16
 271 #define S_R3            12
 272 #define S_R2            8
 273 #define S_R1            4
 274 #define S_R0            0
 275
 276 #define MODE_SVC 0x13
 277 #define I_BIT    0x80
 278
 279 /*
 280  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 281  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 282  */
 283
 284         .macro  bad_save_user_regs
 285         sub     sp, sp, #S_FRAME_SIZE
 286         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 287         add     r8, sp, #S_PC
 288
 289         ldr     r2, _armboot_start
 290         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 291         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 292         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 293         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 294
 295         add     r5, sp, #S_SP
 296         mov     r1, lr
 297         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 298         mov     r0, sp
 299         .endm
 300
 301         .macro  irq_save_user_regs
 302         sub     sp, sp, #S_FRAME_SIZE
 303         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 304         add     r8, sp, #S_PC
 305         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 306         str     lr, [r8, #0]                    @ Save calling PC
 307         mrs     r6, spsr
 308         str     r6, [r8, #4]                    @ Save CPSR
 309         str     r0, [r8, #8]                    @ Save OLD_R0
 310         mov     r0, sp
 311         .endm
 312
 313         .macro  irq_restore_user_regs
 314         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 315         mov     r0, r0
 316         ldr     lr, [sp, #S_PC]                 @ Get PC
 317         add     sp, sp, #S_FRAME_SIZE
 318         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 319         .endm
 320
 321         .macro get_bad_stack
 322         ldr     r13, _armboot_start             @ setup our mode stack
 323         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 324         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 325
 326         str     lr, [r13]                       @ save caller lr / spsr
 327         mrs     lr, spsr
 328         str     lr, [r13, #4]
 329
 330         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 331         msr     spsr_c, r13
 332         mov     lr, pc
 333         movs    pc, lr
 334         .endm
 335
 336         .macro get_irq_stack                    @ setup IRQ stack
 337         ldr     sp, IRQ_STACK_START
 338         .endm
 339
 340         .macro get_fiq_stack                    @ setup FIQ stack
 341         ldr     sp, FIQ_STACK_START
 342         .endm
 343
 344 /*
 345  * exception handlers
 346  */
 347         .align  5
 348 undefined_instruction:
 349         get_bad_stack
 350         bad_save_user_regs
 351         bl      do_undefined_instruction
 352
 353         .align  5
 354 software_interrupt:
 355         get_bad_stack
 356         bad_save_user_regs
 357         bl      do_software_interrupt
 358
 359         .align  5
 360 prefetch_abort:
 361         get_bad_stack
 362         bad_save_user_regs
 363         bl      do_prefetch_abort
 364
 365         .align  5
 366 data_abort:
 367         get_bad_stack
 368         bad_save_user_regs
 369         bl      do_data_abort
 370
 371         .align  5
 372 not_used:
 373         get_bad_stack
 374         bad_save_user_regs
 375         bl      do_not_used
 376
 377 #ifdef CONFIG_USE_IRQ
 378
 379         .align  5
 380 irq:
 381         get_irq_stack
 382         irq_save_user_regs
 383         bl      do_irq
 384         irq_restore_user_regs
 385
 386         .align  5
 387 fiq:
 388         get_fiq_stack
 389         /* someone ought to write a more effiction fiq_save_user_regs */
 390         irq_save_user_regs
 391         bl      do_fiq
 392         irq_restore_user_regs
 393
 394 #else
 395
 396         .align  5
 397 irq:
 398         get_bad_stack
 399         bad_save_user_regs
 400         bl      do_irq
 401
 402         .align  5
 403 fiq:
 404         get_bad_stack
 405         bad_save_user_regs
 406         bl      do_fiq
 407
 408 #endif
 409
 410         .align  5
 411 .globl reset_cpu
 412 reset_cpu:
 413         ldr     r0, RST_BASE
 414         mov     r1, #0x0                        @ set bit 3-0 ...
 415         str     r1, [r0, #RCSR]                 @ ... to clear in RCSR
 416         mov     r1, #0x1
 417         str     r1, [r0, #RSRR]                 @ and perform reset
 418         b       reset_cpu                       @ silly, but repeat endlessly