2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
44 _undefined_instruction: .word undefined_instruction
45 _software_interrupt: .word software_interrupt
46 _prefetch_abort: .word prefetch_abort
47 _data_abort: .word data_abort
48 _not_used: .word not_used
52 .balignl 16,0xdeadbeef
56 * Startup Code (reset vector)
58 * do important init only if we don't start from memory!
59 * - relocate armboot to ram
61 * - jump to second stage
65 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
75 * Note: _armboot_end_data and _armboot_end are defined
76 * by the (board-dependent) linker script.
77 * _armboot_end_data is the first usable FLASH address after armboot
79 .globl _armboot_end_data
81 .word armboot_end_data
87 * This is defined in the board specific linker script
98 * _armboot_real_end is the first usable RAM address behind armboot
99 * and the various stacks
101 .globl _armboot_real_end
106 * We relocate uboot to this address (end of RAM - 128 KiB)
112 #ifdef CONFIG_USE_IRQ
113 /* IRQ stack memory (calculated at run-time) */
114 .globl IRQ_STACK_START
118 /* IRQ stack memory (calculated at run-time) */
119 .globl FIQ_STACK_START
125 /****************************************************************************/
127 /* the actual reset code */
129 /****************************************************************************/
132 mrs r0,cpsr /* set the cpu to SVC32 mode */
133 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
137 bl cpu_init_crit /* we do sys-critical inits */
139 relocate: /* relocate U-Boot to RAM */
140 adr r0, _start /* r0 <- current position of code */
141 ldr r2, _armboot_start
143 sub r2, r3, r2 /* r2 <- size of armboot */
145 add r2, r0, r2 /* r2 <- source end address */
148 ldmia r0!, {r3-r10} /* copy from source address [r0] */
149 stmia r1!, {r3-r10} /* copy to target address [r1] */
150 cmp r0, r2 /* until source end addreee [r2] */
153 /* Set up the stack */
154 ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */
155 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
156 /* FIXME: bdinfo should be here */
157 sub sp, r0, #12 /* leave 3 words for abort-stack */
161 ldr r0, _bss_start /* find start of bss segment */
162 add r0, r0, #4 /* start at first byte of bss */
163 ldr r1, _bss_end /* stop here */
164 mov r2, #0x00000000 /* clear */
166 clbss_l:str r2, [r0] /* clear loop... */
172 ldr pc, _start_armboot
174 _start_armboot: .word start_armboot
177 /****************************************************************************/
179 /* CPU_init_critical registers */
181 /* - setup important registers */
182 /* - setup memory timing */
184 /****************************************************************************/
186 /* Interrupt-Controller base address */
187 IC_BASE: .word 0x40d00000
190 /* Reset-Controller */
191 RST_BASE: .word 0x40f00030
194 /* Operating System Timer */
195 OSTIMER_BASE: .word 0x40a00000
201 /* Clock Manager Registers */
203 CC_BASE: .word 0x41300000
205 cpuspeed: .word CFG_CPUSPEED
223 /* set clock speed */
228 mcr p14, 0, r0, c6, c0, 0
232 * before relocating, we have to setup RAM timing
233 * because memory timing is board-dependend, you will
234 * find a memsetup.S in your board directory.
240 /* Memory interfaces are working. Disable MMU and enable I-cache. */
242 ldr r0, =0x2001 /* enable access to all coproc. */
243 mcr p15, 0, r0, c15, c1, 0
246 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
249 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
252 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
255 /* Enable the Icache */
257 mrc p15, 0, r0, c1, c0, 0
259 mcr p15, 0, r0, c1, c0, 0
265 /****************************************************************************/
267 /* Interrupt handling */
269 /****************************************************************************/
271 /* IRQ stack frame */
273 #define S_FRAME_SIZE 72
295 #define MODE_SVC 0x13
297 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
299 .macro bad_save_user_regs
300 sub sp, sp, #S_FRAME_SIZE
301 stmia sp, {r0 - r12} /* Calling r0-r12 */
305 add r2, r2, #CONFIG_STACKSIZE
307 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
308 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
312 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
317 /* use irq_save_user_regs / irq_restore_user_regs for */
318 /* IRQ/FIQ handling */
320 .macro irq_save_user_regs
321 sub sp, sp, #S_FRAME_SIZE
322 stmia sp, {r0 - r12} /* Calling r0-r12 */
324 stmdb r8, {sp, lr}^ /* Calling SP, LR */
325 str lr, [r8, #0] /* Save calling PC */
327 str r6, [r8, #4] /* Save CPSR */
328 str r0, [r8, #8] /* Save OLD_R0 */
332 .macro irq_restore_user_regs
333 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
335 ldr lr, [sp, #S_PC] @ Get PC
336 add sp, sp, #S_FRAME_SIZE
337 subs pc, lr, #4 @ return & move spsr_svc into cpsr
341 ldr r13, _armboot_end @ setup our mode stack
342 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
345 str lr, [r13] @ save caller lr / spsr
349 mov r13, #MODE_SVC @ prepare SVC-Mode
355 .macro get_irq_stack @ setup IRQ stack
356 ldr sp, IRQ_STACK_START
359 .macro get_fiq_stack @ setup FIQ stack
360 ldr sp, FIQ_STACK_START
364 /****************************************************************************/
366 /* exception handlers */
368 /****************************************************************************/
371 undefined_instruction:
374 bl do_undefined_instruction
380 bl do_software_interrupt
400 #ifdef CONFIG_USE_IRQ
407 irq_restore_user_regs
412 irq_save_user_regs /* someone ought to write a more */
413 bl do_fiq /* effiction fiq_save_user_regs */
414 irq_restore_user_regs
432 /************************************************************************/
434 /* Reset function: the PXA250 has no reset function, so we have to */
435 /* perform a watchdog timeout to cause a reset. */
437 /************************************************************************/
441 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
445 orr r1, r1, #0x0001 /* bit0: WME */
448 /* OS timer does only wrap every 1165 seconds, so we have to set */
449 /* the match register as well. */
451 ldr r1, [r0, #OSCR] /* read OS timer */
452 add r1, r1, #0x800 /* let OSMR3 match after */
453 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */