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[people/ms/u-boot.git] / drivers / block / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 */
10 #include <common.h>
11
12 #include <command.h>
13 #include <dm.h>
14 #include <pci.h>
15 #include <asm/processor.h>
16 #include <asm/errno.h>
17 #include <asm/io.h>
18 #include <malloc.h>
19 #include <memalign.h>
20 #include <scsi.h>
21 #include <libata.h>
22 #include <linux/ctype.h>
23 #include <ahci.h>
24
25 static int ata_io_flush(u8 port);
26
27 struct ahci_probe_ent *probe_ent = NULL;
28 u16 *ataid[AHCI_MAX_PORTS];
29
30 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31
32 /*
33 * Some controllers limit number of blocks they can read/write at once.
34 * Contemporary SSD devices work much faster if the read/write size is aligned
35 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 * needed.
37 */
38 #ifndef MAX_SATA_BLOCKS_READ_WRITE
39 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 #endif
41
42 /* Maximum timeouts for each event */
43 #define WAIT_MS_SPINUP 20000
44 #define WAIT_MS_DATAIO 10000
45 #define WAIT_MS_FLUSH 5000
46 #define WAIT_MS_LINKUP 200
47
48 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
49 {
50 return base + 0x100 + (port * 0x80);
51 }
52
53
54 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
55 unsigned int port_idx)
56 {
57 base = ahci_port_base(base, port_idx);
58
59 port->cmd_addr = base;
60 port->scr_addr = base + PORT_SCR;
61 }
62
63
64 #define msleep(a) udelay(a * 1000)
65
66 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
67 {
68 const unsigned long start = begin;
69 const unsigned long end = start + len;
70
71 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
72 flush_dcache_range(start, end);
73 }
74
75 /*
76 * SATA controller DMAs to physical RAM. Ensure data from the
77 * controller is invalidated from dcache; next access comes from
78 * physical RAM.
79 */
80 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
81 {
82 const unsigned long start = begin;
83 const unsigned long end = start + len;
84
85 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
86 invalidate_dcache_range(start, end);
87 }
88
89 /*
90 * Ensure data for SATA controller is flushed out of dcache and
91 * written to physical memory.
92 */
93 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
94 {
95 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
96 AHCI_PORT_PRIV_DMA_SZ);
97 }
98
99 static int waiting_for_cmd_completed(void __iomem *offset,
100 int timeout_msec,
101 u32 sign)
102 {
103 int i;
104 u32 status;
105
106 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 msleep(1);
108
109 return (i < timeout_msec) ? 0 : -1;
110 }
111
112 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
113 {
114 u32 tmp;
115 int j = 0;
116 void __iomem *port_mmio = probe_ent->port[port].port_mmio;
117
118 /*
119 * Bring up SATA link.
120 * SATA link bringup time is usually less than 1 ms; only very
121 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
122 */
123 while (j < WAIT_MS_LINKUP) {
124 tmp = readl(port_mmio + PORT_SCR_STAT);
125 tmp &= PORT_SCR_STAT_DET_MASK;
126 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
127 return 0;
128 udelay(1000);
129 j++;
130 }
131 return 1;
132 }
133
134 #ifdef CONFIG_SUNXI_AHCI
135 /* The sunxi AHCI controller requires this undocumented setup */
136 static void sunxi_dma_init(void __iomem *port_mmio)
137 {
138 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
139 }
140 #endif
141
142 int ahci_reset(void __iomem *base)
143 {
144 int i = 1000;
145 u32 __iomem *host_ctl_reg = base + HOST_CTL;
146 u32 tmp = readl(host_ctl_reg); /* global controller reset */
147
148 if ((tmp & HOST_RESET) == 0)
149 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
150
151 /*
152 * reset must complete within 1 second, or
153 * the hardware should be considered fried.
154 */
155 do {
156 udelay(1000);
157 tmp = readl(host_ctl_reg);
158 i--;
159 } while ((i > 0) && (tmp & HOST_RESET));
160
161 if (i == 0) {
162 printf("controller reset failed (0x%x)\n", tmp);
163 return -1;
164 }
165
166 return 0;
167 }
168
169 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
170 {
171 #ifndef CONFIG_SCSI_AHCI_PLAT
172 # ifdef CONFIG_DM_PCI
173 struct udevice *dev = probe_ent->dev;
174 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
175 # else
176 pci_dev_t pdev = probe_ent->dev;
177 unsigned short vendor;
178 # endif
179 u16 tmp16;
180 #endif
181 void __iomem *mmio = probe_ent->mmio_base;
182 u32 tmp, cap_save, cmd;
183 int i, j, ret;
184 void __iomem *port_mmio;
185 u32 port_map;
186
187 debug("ahci_host_init: start\n");
188
189 cap_save = readl(mmio + HOST_CAP);
190 cap_save &= ((1 << 28) | (1 << 17));
191 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
192
193 ret = ahci_reset(probe_ent->mmio_base);
194 if (ret)
195 return ret;
196
197 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
198 writel(cap_save, mmio + HOST_CAP);
199 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
200
201 #ifndef CONFIG_SCSI_AHCI_PLAT
202 # ifdef CONFIG_DM_PCI
203 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
204 u16 tmp16;
205
206 dm_pci_read_config16(dev, 0x92, &tmp16);
207 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
208 }
209 # else
210 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
211
212 if (vendor == PCI_VENDOR_ID_INTEL) {
213 u16 tmp16;
214 pci_read_config_word(pdev, 0x92, &tmp16);
215 tmp16 |= 0xf;
216 pci_write_config_word(pdev, 0x92, tmp16);
217 }
218 # endif
219 #endif
220 probe_ent->cap = readl(mmio + HOST_CAP);
221 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
222 port_map = probe_ent->port_map;
223 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
224
225 debug("cap 0x%x port_map 0x%x n_ports %d\n",
226 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
227
228 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
229 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
230
231 for (i = 0; i < probe_ent->n_ports; i++) {
232 if (!(port_map & (1 << i)))
233 continue;
234 probe_ent->port[i].port_mmio = ahci_port_base(mmio, i);
235 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
236 ahci_setup_port(&probe_ent->port[i], mmio, i);
237
238 /* make sure port is not active */
239 tmp = readl(port_mmio + PORT_CMD);
240 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
241 PORT_CMD_FIS_RX | PORT_CMD_START)) {
242 debug("Port %d is active. Deactivating.\n", i);
243 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
244 PORT_CMD_FIS_RX | PORT_CMD_START);
245 writel_with_flush(tmp, port_mmio + PORT_CMD);
246
247 /* spec says 500 msecs for each bit, so
248 * this is slightly incorrect.
249 */
250 msleep(500);
251 }
252
253 #ifdef CONFIG_SUNXI_AHCI
254 sunxi_dma_init(port_mmio);
255 #endif
256
257 /* Add the spinup command to whatever mode bits may
258 * already be on in the command register.
259 */
260 cmd = readl(port_mmio + PORT_CMD);
261 cmd |= PORT_CMD_SPIN_UP;
262 writel_with_flush(cmd, port_mmio + PORT_CMD);
263
264 /* Bring up SATA link. */
265 ret = ahci_link_up(probe_ent, i);
266 if (ret) {
267 printf("SATA link %d timeout.\n", i);
268 continue;
269 } else {
270 debug("SATA link ok.\n");
271 }
272
273 /* Clear error status */
274 tmp = readl(port_mmio + PORT_SCR_ERR);
275 if (tmp)
276 writel(tmp, port_mmio + PORT_SCR_ERR);
277
278 debug("Spinning up device on SATA port %d... ", i);
279
280 j = 0;
281 while (j < WAIT_MS_SPINUP) {
282 tmp = readl(port_mmio + PORT_TFDATA);
283 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
284 break;
285 udelay(1000);
286 tmp = readl(port_mmio + PORT_SCR_STAT);
287 tmp &= PORT_SCR_STAT_DET_MASK;
288 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
289 break;
290 j++;
291 }
292
293 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
294 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
295 debug("SATA link %d down (COMINIT received), retrying...\n", i);
296 i--;
297 continue;
298 }
299
300 printf("Target spinup took %d ms.\n", j);
301 if (j == WAIT_MS_SPINUP)
302 debug("timeout.\n");
303 else
304 debug("ok.\n");
305
306 tmp = readl(port_mmio + PORT_SCR_ERR);
307 debug("PORT_SCR_ERR 0x%x\n", tmp);
308 writel(tmp, port_mmio + PORT_SCR_ERR);
309
310 /* ack any pending irq events for this port */
311 tmp = readl(port_mmio + PORT_IRQ_STAT);
312 debug("PORT_IRQ_STAT 0x%x\n", tmp);
313 if (tmp)
314 writel(tmp, port_mmio + PORT_IRQ_STAT);
315
316 writel(1 << i, mmio + HOST_IRQ_STAT);
317
318 /* register linkup ports */
319 tmp = readl(port_mmio + PORT_SCR_STAT);
320 debug("SATA port %d status: 0x%x\n", i, tmp);
321 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
322 probe_ent->link_port_map |= (0x01 << i);
323 }
324
325 tmp = readl(mmio + HOST_CTL);
326 debug("HOST_CTL 0x%x\n", tmp);
327 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
328 tmp = readl(mmio + HOST_CTL);
329 debug("HOST_CTL 0x%x\n", tmp);
330 #ifndef CONFIG_SCSI_AHCI_PLAT
331 # ifdef CONFIG_DM_PCI
332 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
333 tmp |= PCI_COMMAND_MASTER;
334 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
335 # else
336 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
337 tmp |= PCI_COMMAND_MASTER;
338 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
339 # endif
340 #endif
341 return 0;
342 }
343
344
345 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
346 {
347 #ifndef CONFIG_SCSI_AHCI_PLAT
348 # ifdef CONFIG_DM_PCI
349 struct udevice *dev = probe_ent->dev;
350 # else
351 pci_dev_t pdev = probe_ent->dev;
352 # endif
353 u16 cc;
354 #endif
355 void __iomem *mmio = probe_ent->mmio_base;
356 u32 vers, cap, cap2, impl, speed;
357 const char *speed_s;
358 const char *scc_s;
359
360 vers = readl(mmio + HOST_VERSION);
361 cap = probe_ent->cap;
362 cap2 = readl(mmio + HOST_CAP2);
363 impl = probe_ent->port_map;
364
365 speed = (cap >> 20) & 0xf;
366 if (speed == 1)
367 speed_s = "1.5";
368 else if (speed == 2)
369 speed_s = "3";
370 else if (speed == 3)
371 speed_s = "6";
372 else
373 speed_s = "?";
374
375 #ifdef CONFIG_SCSI_AHCI_PLAT
376 scc_s = "SATA";
377 #else
378 # ifdef CONFIG_DM_PCI
379 dm_pci_read_config16(dev, 0x0a, &cc);
380 # else
381 pci_read_config_word(pdev, 0x0a, &cc);
382 # endif
383 if (cc == 0x0101)
384 scc_s = "IDE";
385 else if (cc == 0x0106)
386 scc_s = "SATA";
387 else if (cc == 0x0104)
388 scc_s = "RAID";
389 else
390 scc_s = "unknown";
391 #endif
392 printf("AHCI %02x%02x.%02x%02x "
393 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
394 (vers >> 24) & 0xff,
395 (vers >> 16) & 0xff,
396 (vers >> 8) & 0xff,
397 vers & 0xff,
398 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
399
400 printf("flags: "
401 "%s%s%s%s%s%s%s"
402 "%s%s%s%s%s%s%s"
403 "%s%s%s%s%s%s\n",
404 cap & (1 << 31) ? "64bit " : "",
405 cap & (1 << 30) ? "ncq " : "",
406 cap & (1 << 28) ? "ilck " : "",
407 cap & (1 << 27) ? "stag " : "",
408 cap & (1 << 26) ? "pm " : "",
409 cap & (1 << 25) ? "led " : "",
410 cap & (1 << 24) ? "clo " : "",
411 cap & (1 << 19) ? "nz " : "",
412 cap & (1 << 18) ? "only " : "",
413 cap & (1 << 17) ? "pmp " : "",
414 cap & (1 << 16) ? "fbss " : "",
415 cap & (1 << 15) ? "pio " : "",
416 cap & (1 << 14) ? "slum " : "",
417 cap & (1 << 13) ? "part " : "",
418 cap & (1 << 7) ? "ccc " : "",
419 cap & (1 << 6) ? "ems " : "",
420 cap & (1 << 5) ? "sxs " : "",
421 cap2 & (1 << 2) ? "apst " : "",
422 cap2 & (1 << 1) ? "nvmp " : "",
423 cap2 & (1 << 0) ? "boh " : "");
424 }
425
426 #ifndef CONFIG_SCSI_AHCI_PLAT
427 # ifdef CONFIG_DM_PCI
428 static int ahci_init_one(struct udevice *dev)
429 # else
430 static int ahci_init_one(pci_dev_t dev)
431 # endif
432 {
433 u16 vendor;
434 int rc;
435
436 probe_ent = malloc(sizeof(struct ahci_probe_ent));
437 if (!probe_ent) {
438 printf("%s: No memory for probe_ent\n", __func__);
439 return -ENOMEM;
440 }
441
442 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
443 probe_ent->dev = dev;
444
445 probe_ent->host_flags = ATA_FLAG_SATA
446 | ATA_FLAG_NO_LEGACY
447 | ATA_FLAG_MMIO
448 | ATA_FLAG_PIO_DMA
449 | ATA_FLAG_NO_ATAPI;
450 probe_ent->pio_mask = 0x1f;
451 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
452
453 #ifdef CONFIG_DM_PCI
454 probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
455 PCI_REGION_MEM);
456
457 /* Take from kernel:
458 * JMicron-specific fixup:
459 * make sure we're in AHCI mode
460 */
461 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
462 if (vendor == 0x197b)
463 dm_pci_write_config8(dev, 0x41, 0xa1);
464 #else
465 probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
466 PCI_REGION_MEM);
467
468 /* Take from kernel:
469 * JMicron-specific fixup:
470 * make sure we're in AHCI mode
471 */
472 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
473 if (vendor == 0x197b)
474 pci_write_config_byte(dev, 0x41, 0xa1);
475 #endif
476
477 debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
478 /* initialize adapter */
479 rc = ahci_host_init(probe_ent);
480 if (rc)
481 goto err_out;
482
483 ahci_print_info(probe_ent);
484
485 return 0;
486
487 err_out:
488 return rc;
489 }
490 #endif
491
492 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
493
494 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
495 {
496 struct ahci_ioports *pp = &(probe_ent->port[port]);
497 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
498 u32 sg_count;
499 int i;
500
501 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
502 if (sg_count > AHCI_MAX_SG) {
503 printf("Error:Too much sg!\n");
504 return -1;
505 }
506
507 for (i = 0; i < sg_count; i++) {
508 ahci_sg->addr =
509 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
510 ahci_sg->addr_hi = 0;
511 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
512 (buf_len < MAX_DATA_BYTE_COUNT
513 ? (buf_len - 1)
514 : (MAX_DATA_BYTE_COUNT - 1)));
515 ahci_sg++;
516 buf_len -= MAX_DATA_BYTE_COUNT;
517 }
518
519 return sg_count;
520 }
521
522
523 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
524 {
525 pp->cmd_slot->opts = cpu_to_le32(opts);
526 pp->cmd_slot->status = 0;
527 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
528 #ifdef CONFIG_PHYS_64BIT
529 pp->cmd_slot->tbl_addr_hi =
530 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
531 #endif
532 }
533
534 static int wait_spinup(void __iomem *port_mmio)
535 {
536 ulong start;
537 u32 tf_data;
538
539 start = get_timer(0);
540 do {
541 tf_data = readl(port_mmio + PORT_TFDATA);
542 if (!(tf_data & ATA_BUSY))
543 return 0;
544 } while (get_timer(start) < WAIT_MS_SPINUP);
545
546 return -ETIMEDOUT;
547 }
548
549 static int ahci_port_start(u8 port)
550 {
551 struct ahci_ioports *pp = &(probe_ent->port[port]);
552 void __iomem *port_mmio = pp->port_mmio;
553 u32 port_status;
554 void __iomem *mem;
555
556 debug("Enter start port: %d\n", port);
557 port_status = readl(port_mmio + PORT_SCR_STAT);
558 debug("Port %d status: %x\n", port, port_status);
559 if ((port_status & 0xf) != 0x03) {
560 printf("No Link on this port!\n");
561 return -1;
562 }
563
564 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
565 if (!mem) {
566 free(pp);
567 printf("%s: No mem for table!\n", __func__);
568 return -ENOMEM;
569 }
570
571 /* Aligned to 2048-bytes */
572 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
573 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
574
575 /*
576 * First item in chunk of DMA memory: 32-slot command table,
577 * 32 bytes each in size
578 */
579 pp->cmd_slot =
580 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
581 debug("cmd_slot = %p\n", pp->cmd_slot);
582 mem += (AHCI_CMD_SLOT_SZ + 224);
583
584 /*
585 * Second item: Received-FIS area
586 */
587 pp->rx_fis = virt_to_phys((void *)mem);
588 mem += AHCI_RX_FIS_SZ;
589
590 /*
591 * Third item: data area for storing a single command
592 * and its scatter-gather table
593 */
594 pp->cmd_tbl = virt_to_phys((void *)mem);
595 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
596
597 mem += AHCI_CMD_TBL_HDR;
598 pp->cmd_tbl_sg =
599 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
600
601 writel_with_flush((unsigned long)pp->cmd_slot,
602 port_mmio + PORT_LST_ADDR);
603
604 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
605
606 #ifdef CONFIG_SUNXI_AHCI
607 sunxi_dma_init(port_mmio);
608 #endif
609
610 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
611 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
612 PORT_CMD_START, port_mmio + PORT_CMD);
613
614 debug("Exit start port %d\n", port);
615
616 /*
617 * Make sure interface is not busy based on error and status
618 * information from task file data register before proceeding
619 */
620 return wait_spinup(port_mmio);
621 }
622
623
624 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
625 int buf_len, u8 is_write)
626 {
627
628 struct ahci_ioports *pp = &(probe_ent->port[port]);
629 void __iomem *port_mmio = pp->port_mmio;
630 u32 opts;
631 u32 port_status;
632 int sg_count;
633
634 debug("Enter %s: for port %d\n", __func__, port);
635
636 if (port > probe_ent->n_ports) {
637 printf("Invalid port number %d\n", port);
638 return -1;
639 }
640
641 port_status = readl(port_mmio + PORT_SCR_STAT);
642 if ((port_status & 0xf) != 0x03) {
643 debug("No Link on port %d!\n", port);
644 return -1;
645 }
646
647 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
648
649 sg_count = ahci_fill_sg(port, buf, buf_len);
650 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
651 ahci_fill_cmd_slot(pp, opts);
652
653 ahci_dcache_flush_sata_cmd(pp);
654 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
655
656 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
657
658 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
659 WAIT_MS_DATAIO, 0x1)) {
660 printf("timeout exit!\n");
661 return -1;
662 }
663
664 ahci_dcache_invalidate_range((unsigned long)buf,
665 (unsigned long)buf_len);
666 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
667
668 return 0;
669 }
670
671
672 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
673 {
674 int i;
675 for (i = 0; i < len / 2; i++)
676 target[i] = swab16(src[i]);
677 return (char *)target;
678 }
679
680 /*
681 * SCSI INQUIRY command operation.
682 */
683 static int ata_scsiop_inquiry(ccb *pccb)
684 {
685 static const u8 hdr[] = {
686 0,
687 0,
688 0x5, /* claim SPC-3 version compatibility */
689 2,
690 95 - 4,
691 };
692 u8 fis[20];
693 u16 *idbuf;
694 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
695 u8 port;
696
697 /* Clean ccb data buffer */
698 memset(pccb->pdata, 0, pccb->datalen);
699
700 memcpy(pccb->pdata, hdr, sizeof(hdr));
701
702 if (pccb->datalen <= 35)
703 return 0;
704
705 memset(fis, 0, sizeof(fis));
706 /* Construct the FIS */
707 fis[0] = 0x27; /* Host to device FIS. */
708 fis[1] = 1 << 7; /* Command FIS. */
709 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
710
711 /* Read id from sata */
712 port = pccb->target;
713
714 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
715 ATA_ID_WORDS * 2, 0)) {
716 debug("scsi_ahci: SCSI inquiry command failure.\n");
717 return -EIO;
718 }
719
720 if (!ataid[port]) {
721 ataid[port] = malloc(ATA_ID_WORDS * 2);
722 if (!ataid[port]) {
723 printf("%s: No memory for ataid[port]\n", __func__);
724 return -ENOMEM;
725 }
726 }
727
728 idbuf = ataid[port];
729
730 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
731 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
732
733 memcpy(&pccb->pdata[8], "ATA ", 8);
734 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
735 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
736
737 #ifdef DEBUG
738 ata_dump_id(idbuf);
739 #endif
740 return 0;
741 }
742
743
744 /*
745 * SCSI READ10/WRITE10 command operation.
746 */
747 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
748 {
749 lbaint_t lba = 0;
750 u16 blocks = 0;
751 u8 fis[20];
752 u8 *user_buffer = pccb->pdata;
753 u32 user_buffer_size = pccb->datalen;
754
755 /* Retrieve the base LBA number from the ccb structure. */
756 if (pccb->cmd[0] == SCSI_READ16) {
757 memcpy(&lba, pccb->cmd + 2, 8);
758 lba = be64_to_cpu(lba);
759 } else {
760 u32 temp;
761 memcpy(&temp, pccb->cmd + 2, 4);
762 lba = be32_to_cpu(temp);
763 }
764
765 /*
766 * Retrieve the base LBA number and the block count from
767 * the ccb structure.
768 *
769 * For 10-byte and 16-byte SCSI R/W commands, transfer
770 * length 0 means transfer 0 block of data.
771 * However, for ATA R/W commands, sector count 0 means
772 * 256 or 65536 sectors, not 0 sectors as in SCSI.
773 *
774 * WARNING: one or two older ATA drives treat 0 as 0...
775 */
776 if (pccb->cmd[0] == SCSI_READ16)
777 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
778 else
779 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
780
781 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
782 is_write ? "write" : "read", blocks, lba);
783
784 /* Preset the FIS */
785 memset(fis, 0, sizeof(fis));
786 fis[0] = 0x27; /* Host to device FIS. */
787 fis[1] = 1 << 7; /* Command FIS. */
788 /* Command byte (read/write). */
789 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
790
791 while (blocks) {
792 u16 now_blocks; /* number of blocks per iteration */
793 u32 transfer_size; /* number of bytes per iteration */
794
795 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
796
797 transfer_size = ATA_SECT_SIZE * now_blocks;
798 if (transfer_size > user_buffer_size) {
799 printf("scsi_ahci: Error: buffer too small.\n");
800 return -EIO;
801 }
802
803 /*
804 * LBA48 SATA command but only use 32bit address range within
805 * that (unless we've enabled 64bit LBA support). The next
806 * smaller command range (28bit) is too small.
807 */
808 fis[4] = (lba >> 0) & 0xff;
809 fis[5] = (lba >> 8) & 0xff;
810 fis[6] = (lba >> 16) & 0xff;
811 fis[7] = 1 << 6; /* device reg: set LBA mode */
812 fis[8] = ((lba >> 24) & 0xff);
813 #ifdef CONFIG_SYS_64BIT_LBA
814 if (pccb->cmd[0] == SCSI_READ16) {
815 fis[9] = ((lba >> 32) & 0xff);
816 fis[10] = ((lba >> 40) & 0xff);
817 }
818 #endif
819
820 fis[3] = 0xe0; /* features */
821
822 /* Block (sector) count */
823 fis[12] = (now_blocks >> 0) & 0xff;
824 fis[13] = (now_blocks >> 8) & 0xff;
825
826 /* Read/Write from ahci */
827 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
828 user_buffer, transfer_size,
829 is_write)) {
830 debug("scsi_ahci: SCSI %s10 command failure.\n",
831 is_write ? "WRITE" : "READ");
832 return -EIO;
833 }
834
835 /* If this transaction is a write, do a following flush.
836 * Writes in u-boot are so rare, and the logic to know when is
837 * the last write and do a flush only there is sufficiently
838 * difficult. Just do a flush after every write. This incurs,
839 * usually, one extra flush when the rare writes do happen.
840 */
841 if (is_write) {
842 if (-EIO == ata_io_flush(pccb->target))
843 return -EIO;
844 }
845 user_buffer += transfer_size;
846 user_buffer_size -= transfer_size;
847 blocks -= now_blocks;
848 lba += now_blocks;
849 }
850
851 return 0;
852 }
853
854
855 /*
856 * SCSI READ CAPACITY10 command operation.
857 */
858 static int ata_scsiop_read_capacity10(ccb *pccb)
859 {
860 u32 cap;
861 u64 cap64;
862 u32 block_size;
863
864 if (!ataid[pccb->target]) {
865 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
866 "\tNo ATA info!\n"
867 "\tPlease run SCSI command INQUIRY first!\n");
868 return -EPERM;
869 }
870
871 cap64 = ata_id_n_sectors(ataid[pccb->target]);
872 if (cap64 > 0x100000000ULL)
873 cap64 = 0xffffffff;
874
875 cap = cpu_to_be32(cap64);
876 memcpy(pccb->pdata, &cap, sizeof(cap));
877
878 block_size = cpu_to_be32((u32)512);
879 memcpy(&pccb->pdata[4], &block_size, 4);
880
881 return 0;
882 }
883
884
885 /*
886 * SCSI READ CAPACITY16 command operation.
887 */
888 static int ata_scsiop_read_capacity16(ccb *pccb)
889 {
890 u64 cap;
891 u64 block_size;
892
893 if (!ataid[pccb->target]) {
894 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
895 "\tNo ATA info!\n"
896 "\tPlease run SCSI command INQUIRY first!\n");
897 return -EPERM;
898 }
899
900 cap = ata_id_n_sectors(ataid[pccb->target]);
901 cap = cpu_to_be64(cap);
902 memcpy(pccb->pdata, &cap, sizeof(cap));
903
904 block_size = cpu_to_be64((u64)512);
905 memcpy(&pccb->pdata[8], &block_size, 8);
906
907 return 0;
908 }
909
910
911 /*
912 * SCSI TEST UNIT READY command operation.
913 */
914 static int ata_scsiop_test_unit_ready(ccb *pccb)
915 {
916 return (ataid[pccb->target]) ? 0 : -EPERM;
917 }
918
919
920 int scsi_exec(ccb *pccb)
921 {
922 int ret;
923
924 switch (pccb->cmd[0]) {
925 case SCSI_READ16:
926 case SCSI_READ10:
927 ret = ata_scsiop_read_write(pccb, 0);
928 break;
929 case SCSI_WRITE10:
930 ret = ata_scsiop_read_write(pccb, 1);
931 break;
932 case SCSI_RD_CAPAC10:
933 ret = ata_scsiop_read_capacity10(pccb);
934 break;
935 case SCSI_RD_CAPAC16:
936 ret = ata_scsiop_read_capacity16(pccb);
937 break;
938 case SCSI_TST_U_RDY:
939 ret = ata_scsiop_test_unit_ready(pccb);
940 break;
941 case SCSI_INQUIRY:
942 ret = ata_scsiop_inquiry(pccb);
943 break;
944 default:
945 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
946 return false;
947 }
948
949 if (ret) {
950 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
951 return false;
952 }
953 return true;
954
955 }
956
957
958 void scsi_low_level_init(int busdevfunc)
959 {
960 int i;
961 u32 linkmap;
962
963 #ifndef CONFIG_SCSI_AHCI_PLAT
964 # ifdef CONFIG_DM_PCI
965 struct udevice *dev;
966 int ret;
967
968 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
969 if (ret)
970 return;
971 ahci_init_one(dev);
972 # else
973 ahci_init_one(busdevfunc);
974 # endif
975 #endif
976
977 linkmap = probe_ent->link_port_map;
978
979 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
980 if (((linkmap >> i) & 0x01)) {
981 if (ahci_port_start((u8) i)) {
982 printf("Can not start port %d\n", i);
983 continue;
984 }
985 }
986 }
987 }
988
989 #ifdef CONFIG_SCSI_AHCI_PLAT
990 int ahci_init(void __iomem *base)
991 {
992 int i, rc = 0;
993 u32 linkmap;
994
995 probe_ent = malloc(sizeof(struct ahci_probe_ent));
996 if (!probe_ent) {
997 printf("%s: No memory for probe_ent\n", __func__);
998 return -ENOMEM;
999 }
1000
1001 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
1002
1003 probe_ent->host_flags = ATA_FLAG_SATA
1004 | ATA_FLAG_NO_LEGACY
1005 | ATA_FLAG_MMIO
1006 | ATA_FLAG_PIO_DMA
1007 | ATA_FLAG_NO_ATAPI;
1008 probe_ent->pio_mask = 0x1f;
1009 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1010
1011 probe_ent->mmio_base = base;
1012
1013 /* initialize adapter */
1014 rc = ahci_host_init(probe_ent);
1015 if (rc)
1016 goto err_out;
1017
1018 ahci_print_info(probe_ent);
1019
1020 linkmap = probe_ent->link_port_map;
1021
1022 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
1023 if (((linkmap >> i) & 0x01)) {
1024 if (ahci_port_start((u8) i)) {
1025 printf("Can not start port %d\n", i);
1026 continue;
1027 }
1028 }
1029 }
1030 err_out:
1031 return rc;
1032 }
1033
1034 void __weak scsi_init(void)
1035 {
1036 }
1037
1038 #endif
1039
1040 /*
1041 * In the general case of generic rotating media it makes sense to have a
1042 * flush capability. It probably even makes sense in the case of SSDs because
1043 * one cannot always know for sure what kind of internal cache/flush mechanism
1044 * is embodied therein. At first it was planned to invoke this after the last
1045 * write to disk and before rebooting. In practice, knowing, a priori, which
1046 * is the last write is difficult. Because writing to the disk in u-boot is
1047 * very rare, this flush command will be invoked after every block write.
1048 */
1049 static int ata_io_flush(u8 port)
1050 {
1051 u8 fis[20];
1052 struct ahci_ioports *pp = &(probe_ent->port[port]);
1053 void __iomem *port_mmio = pp->port_mmio;
1054 u32 cmd_fis_len = 5; /* five dwords */
1055
1056 /* Preset the FIS */
1057 memset(fis, 0, 20);
1058 fis[0] = 0x27; /* Host to device FIS. */
1059 fis[1] = 1 << 7; /* Command FIS. */
1060 fis[2] = ATA_CMD_FLUSH_EXT;
1061
1062 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1063 ahci_fill_cmd_slot(pp, cmd_fis_len);
1064 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1065
1066 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1067 WAIT_MS_FLUSH, 0x1)) {
1068 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1069 return -EIO;
1070 }
1071
1072 return 0;
1073 }
1074
1075
1076 __weak void scsi_bus_reset(void)
1077 {
1078 /*Not implement*/
1079 }
1080
1081 void scsi_print_error(ccb * pccb)
1082 {
1083 /*The ahci error info can be read in the ahci driver*/
1084 }
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