drivers/block/sata_sil3114.h

   1 /*
   2  * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
   3  * Author: Tor Krill <tor@excito.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef SATA_SIL3114_H
  22 #define SATA_SIL3114_H
  23
  24 struct sata_ioports {
  25         unsigned long cmd_addr;
  26         unsigned long data_addr;
  27         unsigned long error_addr;
  28         unsigned long feature_addr;
  29         unsigned long nsect_addr;
  30         unsigned long lbal_addr;
  31         unsigned long lbam_addr;
  32         unsigned long lbah_addr;
  33         unsigned long device_addr;
  34         unsigned long status_addr;
  35         unsigned long command_addr;
  36         unsigned long altstatus_addr;
  37         unsigned long ctl_addr;
  38         unsigned long bmdma_addr;
  39         unsigned long scr_addr;
  40 };
  41
  42 struct sata_port {
  43         unsigned char port_no;  /* primary=0, secondary=1       */
  44         struct sata_ioports ioaddr;     /* ATA cmd/ctl/dma reg blks     */
  45         unsigned char ctl_reg;
  46         unsigned char last_ctl;
  47         unsigned char port_state;       /* 1-port is available and      */
  48         /* 0-port is not available      */
  49         unsigned char dev_mask;
  50 };
  51
  52 /* Missing ata defines */
  53 #define ATA_CMD_STANDBY                 0xE2
  54 #define ATA_CMD_STANDBYNOW1             0xE0
  55 #define ATA_CMD_IDLE                    0xE3
  56 #define ATA_CMD_IDLEIMMEDIATE   0xE1
  57
  58 /* Defines for SIL3114 chip */
  59
  60 /* PCI defines */
  61 #define SIL_VEND_ID             0x1095
  62 #define SIL3114_DEVICE_ID       0x3114
  63
  64 /* some vendor specific registers */
  65 #define VND_SYSCONFSTAT 0x88    /* System Configuration Status and Command */
  66 #define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
  67 #define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
  68 #define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
  69 #define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
  70
  71 /* internal registers mapped by BAR5 */
  72 /* SATA Control*/
  73 #define VND_SCONTROL_CH0        0x100
  74 #define VND_SCONTROL_CH1        0x180
  75 #define VND_SCONTROL_CH2        0x300
  76 #define VND_SCONTROL_CH3        0x380
  77
  78 #define SATA_SC_IPM_T2P         (1<<16)
  79 #define SATA_SC_IPM_T2S         (2<<16)
  80 #define SATA_SC_SPD_1_5         (1<<4)
  81 #define SATA_SC_SPD_3_0         (2<<4)
  82 #define SATA_SC_DET_RST         (1)     /* ATA Reset sequence */
  83 #define SATA_SC_DET_PDIS        (4)     /* PHY Disable */
  84
  85 /* SATA Status */
  86 #define VND_SSTATUS_CH0         0x104
  87 #define VND_SSTATUS_CH1         0x184
  88 #define VND_SSTATUS_CH2         0x304
  89 #define VND_SSTATUS_CH3         0x384
  90
  91 #define SATA_SS_IPM_ACTIVE      (1<<8)
  92 #define SATA_SS_IPM_PARTIAL     (2<<8)
  93 #define SATA_SS_IPM_SLUMBER     (6<<8)
  94 #define SATA_SS_SPD_1_5         (1<<4)
  95 #define SATA_SS_SPD_3_0         (2<<4)
  96 #define SATA_DET_P_NOPHY        (1)     /* Device presence but no PHY connection established */
  97 #define SATA_DET_PRES           (3)     /* Device presence and active PHY */
  98 #define SATA_DET_OFFLINE        (4)     /* Device offline or in loopback mode */
  99
 100 /* Task file registers in BAR5 mapping */
 101 #define VND_TF0_CH0                     0x80
 102 #define VND_TF0_CH1                     0xc0
 103 #define VND_TF0_CH2                     0x280
 104 #define VND_TF0_CH3                     0x2c0
 105 #define VND_TF1_CH0                     0x88
 106 #define VND_TF1_CH1                     0xc8
 107 #define VND_TF1_CH2                     0x288
 108 #define VND_TF1_CH3                     0x2c8
 109 #define VND_TF2_CH0                     0x88
 110 #define VND_TF2_CH1                     0xc8
 111 #define VND_TF2_CH2                     0x288
 112 #define VND_TF2_CH3                     0x2c8
 113
 114 #define VND_BMDMA_CH0           0x00
 115 #define VND_BMDMA_CH1           0x08
 116 #define VND_BMDMA_CH2           0x200
 117 #define VND_BMDMA_CH3           0x208
 118 #define VND_BMDMA2_CH0          0x10
 119 #define VND_BMDMA2_CH1          0x18
 120 #define VND_BMDMA2_CH2          0x210
 121 #define VND_BMDMA2_CH3          0x218
 122
 123 /* FIFO control */
 124 #define VND_FIFOCFG_CH0         0x40
 125 #define VND_FIFOCFG_CH1         0x44
 126 #define VND_FIFOCFG_CH2         0x240
 127 #define VND_FIFOCFG_CH3         0x244
 128
 129 /* Task File configuration and status */
 130 #define VND_TF_CNST_CH0         0xa0
 131 #define VND_TF_CNST_CH1         0xe0
 132 #define VND_TF_CNST_CH2         0x2a0
 133 #define VND_TF_CNST_CH3         0x2e0
 134
 135 #define VND_TF_CNST_BFCMD       (1<<1)
 136 #define VND_TF_CNST_CHNRST      (1<<2)
 137 #define VND_TF_CNST_VDMA        (1<<10)
 138 #define VND_TF_CNST_INTST       (1<<11)
 139 #define VND_TF_CNST_WDTO        (1<<12)
 140 #define VND_TF_CNST_WDEN        (1<<13)
 141 #define VND_TF_CNST_WDIEN       (1<<14)
 142
 143 /* for testing */
 144 #define VND_SSDR                        0x04c   /* System Software Data Register */
 145 #define VND_FMACS                       0x050   /* Flash Memory Address control and status */
 146
 147 #endif