2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
10 #include <dm/device.h>
12 #include <mach/at91_pmc.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 #define GENERATED_SOURCE_MAX 6
18 #define GENERATED_MAX_DIV 255
21 * generated_clk_bind() - for the generated clock driver
22 * Recursively bind its children as clk devices.
24 * @return: 0 on success, or negative error code on failure
26 static int generated_clk_bind(struct udevice
*dev
)
28 return at91_clk_sub_device_bind(dev
, "generic-clk");
31 static const struct udevice_id generated_clk_match
[] = {
32 { .compatible
= "atmel,sama5d2-clk-generated" },
36 U_BOOT_DRIVER(generated_clk
) = {
37 .name
= "generated-clk",
39 .of_match
= generated_clk_match
,
40 .bind
= generated_clk_bind
,
43 /*-------------------------------------------------------------*/
45 struct generic_clk_priv
{
49 static ulong
generic_clk_get_rate(struct clk
*clk
)
51 struct pmc_platdata
*plat
= dev_get_platdata(clk
->dev
);
52 struct at91_pmc
*pmc
= plat
->reg_base
;
59 writel(clk
->id
& AT91_PMC_PCR_PID_MASK
, &pmc
->pcr
);
60 tmp
= readl(&pmc
->pcr
);
61 parent_id
= (tmp
>> AT91_PMC_PCR_GCKCSS_OFFSET
) &
62 AT91_PMC_PCR_GCKCSS_MASK
;
63 gckdiv
= (tmp
>> AT91_PMC_PCR_GCKDIV_OFFSET
) & AT91_PMC_PCR_GCKDIV_MASK
;
65 ret
= clk_get_by_index(dev_get_parent(clk
->dev
), parent_id
, &parent
);
69 clk_rate
= clk_get_rate(&parent
) / (gckdiv
+ 1);
76 static ulong
generic_clk_set_rate(struct clk
*clk
, ulong rate
)
78 struct pmc_platdata
*plat
= dev_get_platdata(clk
->dev
);
79 struct at91_pmc
*pmc
= plat
->reg_base
;
80 struct generic_clk_priv
*priv
= dev_get_priv(clk
->dev
);
81 struct clk parent
, best_parent
;
82 ulong tmp_rate
, best_rate
= rate
, parent_rate
;
83 int tmp_diff
, best_diff
= -1;
84 u32 div
, best_div
= 0;
85 u8 best_parent_id
= 0;
90 for (i
= 0; i
< priv
->num_parents
; i
++) {
91 ret
= clk_get_by_index(dev_get_parent(clk
->dev
), i
, &parent
);
95 parent_rate
= clk_get_rate(&parent
);
96 if (IS_ERR_VALUE(parent_rate
))
99 for (div
= 1; div
< GENERATED_MAX_DIV
+ 2; div
++) {
100 tmp_rate
= DIV_ROUND_CLOSEST(parent_rate
, div
);
103 tmp_diff
= rate
- tmp_rate
;
105 if (best_diff
< 0 || best_diff
> tmp_diff
) {
106 best_rate
= tmp_rate
;
107 best_diff
= tmp_diff
;
110 best_parent
= parent
;
114 if (!best_diff
|| tmp_rate
< rate
)
122 debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
123 best_parent
.dev
->name
, best_rate
, best_div
);
125 ret
= clk_enable(&best_parent
);
129 writel(clk
->id
& AT91_PMC_PCR_PID_MASK
, &pmc
->pcr
);
130 tmp
= readl(&pmc
->pcr
);
131 tmp
&= ~(AT91_PMC_PCR_GCKDIV
| AT91_PMC_PCR_GCKCSS
);
132 tmp
|= AT91_PMC_PCR_GCKCSS_(best_parent_id
) |
133 AT91_PMC_PCR_CMD_WRITE
|
134 AT91_PMC_PCR_GCKDIV_(best_div
) |
136 writel(tmp
, &pmc
->pcr
);
138 while (!(readl(&pmc
->sr
) & AT91_PMC_GCKRDY
))
144 static struct clk_ops generic_clk_ops
= {
145 .of_xlate
= at91_clk_of_xlate
,
146 .get_rate
= generic_clk_get_rate
,
147 .set_rate
= generic_clk_set_rate
,
150 static int generic_clk_ofdata_to_platdata(struct udevice
*dev
)
152 struct generic_clk_priv
*priv
= dev_get_priv(dev
);
153 u32 cells
[GENERATED_SOURCE_MAX
];
156 num_parents
= fdtdec_get_int_array_count(gd
->fdt_blob
,
157 dev_get_parent(dev
)->of_offset
,
159 GENERATED_SOURCE_MAX
);
164 priv
->num_parents
= num_parents
;
169 U_BOOT_DRIVER(generic_clk
) = {
170 .name
= "generic-clk",
172 .probe
= at91_clk_probe
,
173 .ofdata_to_platdata
= generic_clk_ofdata_to_platdata
,
174 .priv_auto_alloc_size
= sizeof(struct generic_clk_priv
),
175 .platdata_auto_alloc_size
= sizeof(struct pmc_platdata
),
176 .ops
= &generic_clk_ops
,