2 * (C) Copyright 2015 Google, Inc
3 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3188.h>
18 #include <asm/arch/grf_rk3188.h>
19 #include <asm/arch/hardware.h>
20 #include <dt-bindings/clock/rk3188-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/log2.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 enum rk3188_clk_type
{
33 struct rk3188_clk_plat
{
34 #if CONFIG_IS_ENABLED(OF_PLATDATA)
35 struct dtd_rockchip_rk3188_cru dtd
;
46 VCO_MAX_HZ
= 2200U * 1000000,
47 VCO_MIN_HZ
= 440 * 1000000,
48 OUTPUT_MAX_HZ
= 2200U * 1000000,
49 OUTPUT_MIN_HZ
= 30 * 1000000,
50 FREF_MAX_HZ
= 2200U * 1000000,
51 FREF_MIN_HZ
= 30 * 1000,
62 PLL_BWADJ_MASK
= 0x0fff,
68 SOCSTS_DPLL_LOCK
= 1 << 5,
69 SOCSTS_APLL_LOCK
= 1 << 6,
70 SOCSTS_CPLL_LOCK
= 1 << 7,
71 SOCSTS_GPLL_LOCK
= 1 << 8,
74 #define RATE_TO_DIV(input_rate, output_rate) \
75 ((input_rate) / (output_rate) - 1);
77 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
79 #define PLL_DIVISORS(hz, _nr, _no) {\
80 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
81 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
82 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
83 "divisors on line " __stringify(__LINE__));
85 /* Keep divisors as low as possible to reduce jitter and power usage */
86 #ifdef CONFIG_SPL_BUILD
87 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2);
88 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 2);
91 static int rkclk_set_pll(struct rk3188_cru
*cru
, enum rk_clk_id clk_id
,
92 const struct pll_div
*div
, bool has_bwadj
)
94 int pll_id
= rk_pll_id(clk_id
);
95 struct rk3188_pll
*pll
= &cru
->pll
[pll_id
];
96 /* All PLLs have same VCO and output frequency range restrictions. */
97 uint vco_hz
= OSC_HZ
/ 1000 * div
->nf
/ div
->nr
* 1000;
98 uint output_hz
= vco_hz
/ div
->no
;
100 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
101 (uint
)pll
, div
->nf
, div
->nr
, div
->no
, vco_hz
, output_hz
);
102 assert(vco_hz
>= VCO_MIN_HZ
&& vco_hz
<= VCO_MAX_HZ
&&
103 output_hz
>= OUTPUT_MIN_HZ
&& output_hz
<= OUTPUT_MAX_HZ
&&
104 (div
->no
== 1 || !(div
->no
% 2)));
107 rk_setreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
109 rk_clrsetreg(&pll
->con0
,
110 CLKR_MASK
<< CLKR_SHIFT
| PLL_OD_MASK
,
111 ((div
->nr
- 1) << CLKR_SHIFT
) | (div
->no
- 1));
112 rk_clrsetreg(&pll
->con1
, CLKF_MASK
, div
->nf
- 1);
115 rk_clrsetreg(&pll
->con2
, PLL_BWADJ_MASK
, (div
->nf
>> 1) - 1);
119 /* return from reset */
120 rk_clrreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
125 static int rkclk_configure_ddr(struct rk3188_cru
*cru
, struct rk3188_grf
*grf
,
126 unsigned int hz
, bool has_bwadj
)
128 static const struct pll_div dpll_cfg
[] = {
129 {.nf
= 25, .nr
= 2, .no
= 1},
130 {.nf
= 400, .nr
= 9, .no
= 2},
131 {.nf
= 500, .nr
= 9, .no
= 2},
132 {.nf
= 100, .nr
= 3, .no
= 1},
140 case 533000000: /* actually 533.3P MHz */
143 case 666000000: /* actually 666.6P MHz */
150 debug("Unsupported SDRAM frequency");
154 /* pll enter slow-mode */
155 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
156 DPLL_MODE_SLOW
<< DPLL_MODE_SHIFT
);
158 rkclk_set_pll(cru
, CLK_DDR
, &dpll_cfg
[cfg
], has_bwadj
);
160 /* wait for pll lock */
161 while (!(readl(&grf
->soc_status0
) & SOCSTS_DPLL_LOCK
))
164 /* PLL enter normal-mode */
165 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
166 DPLL_MODE_NORMAL
<< DPLL_MODE_SHIFT
);
171 static int rkclk_configure_cpu(struct rk3188_cru
*cru
, struct rk3188_grf
*grf
,
172 unsigned int hz
, bool has_bwadj
)
174 static const struct pll_div apll_cfg
[] = {
175 {.nf
= 50, .nr
= 1, .no
= 2},
176 {.nf
= 67, .nr
= 1, .no
= 1},
178 int div_core_peri
, div_aclk_core
, cfg
;
181 * We support two possible frequencies, the safe 600MHz
182 * which will work with default pmic settings and will
183 * be set in SPL to get away from the 24MHz default and
184 * the maximum of 1.6Ghz, which boards can set if they
185 * were able to get pmic support for it.
199 debug("Unsupported ARMCLK frequency");
203 /* pll enter slow-mode */
204 rk_clrsetreg(&cru
->cru_mode_con
, APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
205 APLL_MODE_SLOW
<< APLL_MODE_SHIFT
);
207 rkclk_set_pll(cru
, CLK_ARM
, &apll_cfg
[cfg
], has_bwadj
);
209 /* waiting for pll lock */
210 while (!(readl(&grf
->soc_status0
) & SOCSTS_APLL_LOCK
))
213 /* Set divider for peripherals attached to the cpu core. */
214 rk_clrsetreg(&cru
->cru_clksel_con
[0],
215 CORE_PERI_DIV_MASK
<< CORE_PERI_DIV_SHIFT
,
216 div_core_peri
<< CORE_PERI_DIV_SHIFT
);
218 /* set up dependent divisor for aclk_core */
219 rk_clrsetreg(&cru
->cru_clksel_con
[1],
220 CORE_ACLK_DIV_MASK
<< CORE_ACLK_DIV_SHIFT
,
221 div_aclk_core
<< CORE_ACLK_DIV_SHIFT
);
223 /* PLL enter normal-mode */
224 rk_clrsetreg(&cru
->cru_mode_con
, APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
225 APLL_MODE_NORMAL
<< APLL_MODE_SHIFT
);
230 /* Get pll rate by id */
231 static uint32_t rkclk_pll_get_rate(struct rk3188_cru
*cru
,
232 enum rk_clk_id clk_id
)
236 int pll_id
= rk_pll_id(clk_id
);
237 struct rk3188_pll
*pll
= &cru
->pll
[pll_id
];
238 static u8 clk_shift
[CLK_COUNT
] = {
239 0xff, APLL_MODE_SHIFT
, DPLL_MODE_SHIFT
, CPLL_MODE_SHIFT
,
244 con
= readl(&cru
->cru_mode_con
);
245 shift
= clk_shift
[clk_id
];
246 switch ((con
>> shift
) & APLL_MODE_MASK
) {
249 case APLL_MODE_NORMAL
:
251 con
= readl(&pll
->con0
);
252 no
= ((con
>> CLKOD_SHIFT
) & CLKOD_MASK
) + 1;
253 nr
= ((con
>> CLKR_SHIFT
) & CLKR_MASK
) + 1;
254 con
= readl(&pll
->con1
);
255 nf
= ((con
>> CLKF_SHIFT
) & CLKF_MASK
) + 1;
257 return (24 * nf
/ (nr
* no
)) * 1000000;
264 static ulong
rockchip_mmc_get_clk(struct rk3188_cru
*cru
, uint gclk_rate
,
272 con
= readl(&cru
->cru_clksel_con
[12]);
273 div
= (con
>> EMMC_DIV_SHIFT
) & EMMC_DIV_MASK
;
276 con
= readl(&cru
->cru_clksel_con
[11]);
277 div
= (con
>> MMC0_DIV_SHIFT
) & MMC0_DIV_MASK
;
280 con
= readl(&cru
->cru_clksel_con
[12]);
281 div
= (con
>> SDIO_DIV_SHIFT
) & SDIO_DIV_MASK
;
287 return DIV_TO_RATE(gclk_rate
, div
);
290 static ulong
rockchip_mmc_set_clk(struct rk3188_cru
*cru
, uint gclk_rate
,
291 int periph
, uint freq
)
295 debug("%s: gclk_rate=%u\n", __func__
, gclk_rate
);
296 src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
297 assert(src_clk_div
<= 0x3f);
301 rk_clrsetreg(&cru
->cru_clksel_con
[12],
302 EMMC_DIV_MASK
<< EMMC_DIV_SHIFT
,
303 src_clk_div
<< EMMC_DIV_SHIFT
);
306 rk_clrsetreg(&cru
->cru_clksel_con
[11],
307 MMC0_DIV_MASK
<< MMC0_DIV_SHIFT
,
308 src_clk_div
<< MMC0_DIV_SHIFT
);
311 rk_clrsetreg(&cru
->cru_clksel_con
[12],
312 SDIO_DIV_MASK
<< SDIO_DIV_SHIFT
,
313 src_clk_div
<< SDIO_DIV_SHIFT
);
319 return rockchip_mmc_get_clk(cru
, gclk_rate
, periph
);
322 static ulong
rockchip_spi_get_clk(struct rk3188_cru
*cru
, uint gclk_rate
,
330 con
= readl(&cru
->cru_clksel_con
[25]);
331 div
= (con
>> SPI0_DIV_SHIFT
) & SPI0_DIV_MASK
;
334 con
= readl(&cru
->cru_clksel_con
[25]);
335 div
= (con
>> SPI1_DIV_SHIFT
) & SPI1_DIV_MASK
;
341 return DIV_TO_RATE(gclk_rate
, div
);
344 static ulong
rockchip_spi_set_clk(struct rk3188_cru
*cru
, uint gclk_rate
,
345 int periph
, uint freq
)
347 int src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
351 assert(src_clk_div
<= SPI0_DIV_MASK
);
352 rk_clrsetreg(&cru
->cru_clksel_con
[25],
353 SPI0_DIV_MASK
<< SPI0_DIV_SHIFT
,
354 src_clk_div
<< SPI0_DIV_SHIFT
);
357 assert(src_clk_div
<= SPI1_DIV_MASK
);
358 rk_clrsetreg(&cru
->cru_clksel_con
[25],
359 SPI1_DIV_MASK
<< SPI1_DIV_SHIFT
,
360 src_clk_div
<< SPI1_DIV_SHIFT
);
366 return rockchip_spi_get_clk(cru
, gclk_rate
, periph
);
369 #ifdef CONFIG_SPL_BUILD
370 static void rkclk_init(struct rk3188_cru
*cru
, struct rk3188_grf
*grf
,
373 u32 aclk_div
, hclk_div
, pclk_div
, h2p_div
;
375 /* pll enter slow-mode */
376 rk_clrsetreg(&cru
->cru_mode_con
,
377 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
378 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
379 GPLL_MODE_SLOW
<< GPLL_MODE_SHIFT
|
380 CPLL_MODE_SLOW
<< CPLL_MODE_SHIFT
);
383 rkclk_set_pll(cru
, CLK_GENERAL
, &gpll_init_cfg
, has_bwadj
);
384 rkclk_set_pll(cru
, CLK_CODEC
, &cpll_init_cfg
, has_bwadj
);
386 /* waiting for pll lock */
387 while ((readl(&grf
->soc_status0
) &
388 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
)) !=
389 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
))
393 * cpu clock pll source selection and
394 * reparent aclk_cpu_pre from apll to gpll
395 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
397 aclk_div
= RATE_TO_DIV(GPLL_HZ
, CPU_ACLK_HZ
);
398 assert((aclk_div
+ 1) * CPU_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
400 rk_clrsetreg(&cru
->cru_clksel_con
[0],
401 CPU_ACLK_PLL_MASK
<< CPU_ACLK_PLL_SHIFT
|
402 A9_CPU_DIV_MASK
<< A9_CPU_DIV_SHIFT
,
403 CPU_ACLK_PLL_SELECT_GPLL
<< CPU_ACLK_PLL_SHIFT
|
404 aclk_div
<< A9_CPU_DIV_SHIFT
);
406 hclk_div
= ilog2(CPU_ACLK_HZ
/ CPU_HCLK_HZ
);
407 assert((1 << hclk_div
) * CPU_HCLK_HZ
== CPU_ACLK_HZ
&& hclk_div
< 0x3);
408 pclk_div
= ilog2(CPU_ACLK_HZ
/ CPU_PCLK_HZ
);
409 assert((1 << pclk_div
) * CPU_PCLK_HZ
== CPU_ACLK_HZ
&& pclk_div
< 0x4);
410 h2p_div
= ilog2(CPU_HCLK_HZ
/ CPU_H2P_HZ
);
411 assert((1 << h2p_div
) * CPU_H2P_HZ
== CPU_HCLK_HZ
&& pclk_div
< 0x3);
413 rk_clrsetreg(&cru
->cru_clksel_con
[1],
414 AHB2APB_DIV_MASK
<< AHB2APB_DIV_SHIFT
|
415 CPU_PCLK_DIV_MASK
<< CPU_PCLK_DIV_SHIFT
|
416 CPU_HCLK_DIV_MASK
<< CPU_HCLK_DIV_SHIFT
,
417 h2p_div
<< AHB2APB_DIV_SHIFT
|
418 pclk_div
<< CPU_PCLK_DIV_SHIFT
|
419 hclk_div
<< CPU_HCLK_DIV_SHIFT
);
422 * peri clock pll source selection and
423 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
425 aclk_div
= GPLL_HZ
/ PERI_ACLK_HZ
- 1;
426 assert((aclk_div
+ 1) * PERI_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
428 hclk_div
= ilog2(PERI_ACLK_HZ
/ PERI_HCLK_HZ
);
429 assert((1 << hclk_div
) * PERI_HCLK_HZ
==
430 PERI_ACLK_HZ
&& (hclk_div
< 0x4));
432 pclk_div
= ilog2(PERI_ACLK_HZ
/ PERI_PCLK_HZ
);
433 assert((1 << pclk_div
) * PERI_PCLK_HZ
==
434 PERI_ACLK_HZ
&& (pclk_div
< 0x4));
436 rk_clrsetreg(&cru
->cru_clksel_con
[10],
437 PERI_PCLK_DIV_MASK
<< PERI_PCLK_DIV_SHIFT
|
438 PERI_HCLK_DIV_MASK
<< PERI_HCLK_DIV_SHIFT
|
439 PERI_ACLK_DIV_MASK
<< PERI_ACLK_DIV_SHIFT
,
440 PERI_SEL_GPLL
<< PERI_SEL_PLL_SHIFT
|
441 pclk_div
<< PERI_PCLK_DIV_SHIFT
|
442 hclk_div
<< PERI_HCLK_DIV_SHIFT
|
443 aclk_div
<< PERI_ACLK_DIV_SHIFT
);
445 /* PLL enter normal-mode */
446 rk_clrsetreg(&cru
->cru_mode_con
,
447 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
448 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
449 GPLL_MODE_NORMAL
<< GPLL_MODE_SHIFT
|
450 CPLL_MODE_NORMAL
<< CPLL_MODE_SHIFT
);
452 rockchip_mmc_set_clk(cru
, PERI_HCLK_HZ
, HCLK_SDMMC
, 16000000);
456 static ulong
rk3188_clk_get_rate(struct clk
*clk
)
458 struct rk3188_clk_priv
*priv
= dev_get_priv(clk
->dev
);
459 ulong new_rate
, gclk_rate
;
461 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
464 new_rate
= rkclk_pll_get_rate(priv
->cru
, clk
->id
);
469 new_rate
= rockchip_mmc_get_clk(priv
->cru
, PERI_HCLK_HZ
,
474 new_rate
= rockchip_spi_get_clk(priv
->cru
, PERI_PCLK_HZ
,
490 static ulong
rk3188_clk_set_rate(struct clk
*clk
, ulong rate
)
492 struct rk3188_clk_priv
*priv
= dev_get_priv(clk
->dev
);
493 struct rk3188_cru
*cru
= priv
->cru
;
498 new_rate
= rkclk_configure_cpu(priv
->cru
, priv
->grf
, rate
,
502 new_rate
= rkclk_configure_ddr(priv
->cru
, priv
->grf
, rate
,
508 new_rate
= rockchip_mmc_set_clk(cru
, PERI_HCLK_HZ
,
513 new_rate
= rockchip_spi_set_clk(cru
, PERI_PCLK_HZ
,
523 static struct clk_ops rk3188_clk_ops
= {
524 .get_rate
= rk3188_clk_get_rate
,
525 .set_rate
= rk3188_clk_set_rate
,
528 static int rk3188_clk_ofdata_to_platdata(struct udevice
*dev
)
530 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
531 struct rk3188_clk_priv
*priv
= dev_get_priv(dev
);
533 priv
->cru
= (struct rk3188_cru
*)dev_get_addr(dev
);
539 static int rk3188_clk_probe(struct udevice
*dev
)
541 struct rk3188_clk_priv
*priv
= dev_get_priv(dev
);
542 enum rk3188_clk_type type
= dev_get_driver_data(dev
);
544 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
545 if (IS_ERR(priv
->grf
))
546 return PTR_ERR(priv
->grf
);
547 priv
->has_bwadj
= (type
== RK3188A_CRU
) ? 1 : 0;
549 #ifdef CONFIG_SPL_BUILD
550 #if CONFIG_IS_ENABLED(OF_PLATDATA)
551 struct rk3188_clk_plat
*plat
= dev_get_platdata(dev
);
553 priv
->cru
= map_sysmem(plat
->dtd
.reg
[0], plat
->dtd
.reg
[1]);
556 rkclk_init(priv
->cru
, priv
->grf
, priv
->has_bwadj
);
562 static int rk3188_clk_bind(struct udevice
*dev
)
566 /* The reset driver does not have a device node, so bind it here */
567 ret
= device_bind_driver(gd
->dm_root
, "rk3188_sysreset", "reset", &dev
);
569 debug("Warning: No rk3188 reset driver: ret=%d\n", ret
);
574 static const struct udevice_id rk3188_clk_ids
[] = {
575 { .compatible
= "rockchip,rk3188-cru", .data
= RK3188_CRU
},
576 { .compatible
= "rockchip,rk3188a-cru", .data
= RK3188A_CRU
},
580 U_BOOT_DRIVER(rockchip_rk3188_cru
) = {
581 .name
= "rockchip_rk3188_cru",
583 .of_match
= rk3188_clk_ids
,
584 .priv_auto_alloc_size
= sizeof(struct rk3188_clk_priv
),
585 .platdata_auto_alloc_size
= sizeof(struct rk3188_clk_plat
),
586 .ops
= &rk3188_clk_ops
,
587 .bind
= rk3188_clk_bind
,
588 .ofdata_to_platdata
= rk3188_clk_ofdata_to_platdata
,
589 .probe
= rk3188_clk_probe
,